Eric Vittoz - IEEE

TECHNICAL LITERATURE
Fig. 28: Minimum power consumption P of a CMOS gate
operated in weak inversion (red curve) for an average frequency
f of on/off transition cycles (not to confuse with
the clock frequency). Corresponding optimum supply voltage
V B (black curve).
ring oscillators (that are not very useful circuits). For a
more realistic value α =1/100, the reduction can still be
more than a factor 10, with a maximum possible switching
frequency of about 3MHz for a 0.18 micron process
(which would reach 500MHz for α=1).
This ultimate limit assumes that the off-currents of p- and
n-channel transistors are adjusted to the same value (by
adjusting the source-substrate voltage, which requires a
true twin well process). It might not be reached in practice
due to several side effects like mismatch or drain induced
barrier lowering. The new century has seen the emergence
of a new interest for weak inversion logic (now called subthreshold
logic) with the realization of digital sub-systems
operating at a clock frequency of a few kHz and a supply
voltage of just a few hundred millivolts 58 (see article by J.
Kwong and A. Chandrakasan in this issue). There is no
doubt that further research in this direction (and further
process scaling) will permit an increase in system speed.
But, at ambient temperature, it will never be possible to
decrease the supply voltage much lower (the absolute minimum
for regenerative logic being 2ln(n+1)•U T ). It is interesting
to point out that these voltage levels are comparable
to that of the action potential in the brain.
The human brain is a fantastic computing machine.
With its 10 11 neurons (or 10 12 cells if we include the supporting
glial cells), it consumes about the same power
as a fast modern microprocessor. But its processing
power is immensely larger. It must therefore use much
more energy efficient computation strategies. Some of
them are known. A massive parallelism compensates for
the much lower speed of each neuron (maximum firing
rate of about 2kHz). But it also makes possible the spatio-temporal
representation and processing of information,
by means of arrays of cells organized in maps. The
system may be seen as digital, since it uses short pulses
of fixed shape and amplitude (called the action potential)
to carry the signal. But it is essentially analog since
the information is carried by the frequency and by the
phase of these pulses. Its program and data memory is
distributed and is stored in the pattern of interconnections
and in their variable strengths (synaptic weights).
Its learning capability has inspired the approach of artificial
neural networks (with interesting but limited
results, due probably to an inadequate adaptation to the
silicon environment). But what is known today is certainly
a very small part of all the unusual schemes
exploited by the brain, and new ones are being uncovered
by very active teams of neurophysiologists.
Reducing the power consumption of processing chips
while increasing their complexity will be possible by further
developing traditional techniques, at all levels from
process to software. But there will be limits, beyond
which totally new approaches will be needed. Why not
then try to borrow some of the schemes used by the
brain, thereby harvesting the results of half a billion
years of evolution? Undoubtedly, these schemes will
have to be cleverly adapted to the constraints and possibilities
of the silicon environment. But this adaptation
will only be possible if a sufficient number of openminded
deciders in the industry and in universities
organize a close collaboration of their most inventive circuit
designers with the community of brain researchers.
1 H. J. Oguey “The first quartz wristwatch,” to be published in
IEEE Spectrum.
2 F. M. Wanlass and C. T. Sah, “Nanowatt Logic Using Field-
Effect Metal Oxide Semiconductor Triodes,” ISSCC’63 Digest
of Technical Papers, pp. 32-33, 1963.
3 F. Leuenberger and E. Vittoz, "Complementary MOS lowpower
low-voltage integrated binary counter,” Proc.IEEE,
vol.. 57, No 9, pp 1528-1532, Sept. 1969.
4 A. K. Rapp et al. ”Complementary MOS integrated binary
counter,” ISSCC’67 Digest of Technical Papers, pp. 52-53, 1967.
5 E. Vittoz, W. Hammer, M. Kiener and D. Chauvy, “Logical circuit
for the wristwatch,” Eurocon 1971, Lausanne, paper F2-6.
6 E. Vittoz, "LSI in watches,” Solid-State Circuits 1976, Ed.
Journal de Physique, 1977, Paris. Also published in Pulse,
Jan. 1978, pp. 14-20 (Invited paper ESSCIRC’76).
7 E. Vittoz, C. Piguet and W. Hammer, "Model of the logic
gate,” Proc. Journées d'Electronique 1977, EPF-Lausanne,
pp. 455-467.
8 E. Vittoz, B. Gerber, and F. Leuenberger, "Silicon-gate CMOS
frequency divider for the electronic wrist watch,” IEEE J.
Solid-State Circuits, vol. SC-7, No2, pp. 100-104, April 1972.
9 C. Piguet, “Logic synthesis of race-free asynchronous CMOS
circuits,” IEEE Journal of Solid-State Circuits, vol. 26, No 3,
March 1991, pp. 271-380.
10 E. Vittoz and H. Oguey, "Complementary dynamic logic circuits,”
Electronics Letters, 15th Jan. 1973, vol.9, No 4.
11 H. Oguey and E. Vittoz, “CODYMOS frequency dividers
achieve low power consumption and high frequency,” Electronics
Letters, 23rd August 1973, vol. 9, No 17.
12 R. M. Swanson and J. D. Meindl, “Ion-implanted complementary
MOS transistors in low-voltage circuits," IEEE Journal
of Solid-State Circuits, vol. 7, pp. 146 - 153, April 1972.
13 E. Vittoz and J. Fellrath, “New analog CMOS IC's based on
weak inversion operation,” Proc. ESSCIRC '76, pp. 12-13,
Toulouse, Sept. 1976.
14 E. Vittoz and J. Fellrath, "CMOS analog integrated circuits
based on weak inversion operation,” IEEE J. Solid-State Cir-
22 IEEE SSCS NEWS Summer 2008