Eric Vittoz - IEEE

TECHNICAL LITERATURE
of multi-gate MOS devices and more particularly on
double-gate devices [58], [59].
II. THE EKV DESIGN METHODOLOGY
One of the main features of the EKV model compared
to others is the small number of parameters that it
requires. This obviously simplifies the model and its
implementation, but also the parameter extraction.
Another feature, more important to my eyes, is its
hierarchical structure: indeed the complete compact
model can easily be reduced to the simple hand calculation
model by setting some parameters to specific
values. This allows for a step-by-step approach in
the design of new circuits, starting with the simplest
model coherent with the model used for hand calculation
and progressively adding effects in order to
evaluate their impact on the circuit performance.
Actually, the EKV MOS transistor model was initially
not developed with the aim of having a compact
model for circuit simulation, but rather for having a
simple hand calculation model that can help designing
and sizing circuits that are biased in all modes of
operation including strong and weak inversion but
also the region in between called the moderate inversion.
The available models at that time were simplistic
square-law models that were often inaccurate in
strong inversion and totally wrong in moderate and
weak inversion. The EKV MOS transistor model introduced
the powerful concept of inversion factor (also
called inversion coefficient IC) as the main transistor
design parameter that is more general and replaces
the long-time used overdrive voltage, distinctive of
strong inversion models, but meaningless in weak
inversion. For more than 25 years, E. Vittoz and I have
been teaching analog circuit design based on the use
of this concept of inversion factor. This approach
allows for expressing all the important parameters of
a single transistor biased in saturation, such as smallsignal
parameters, including transconductances and
capacitances, noise parameters, versus a single
parameter: the inversion factor. Sweeping the inversion
factor allows exploring all the design space for a
single transistor. In 1996, I created a first sizing tool
actually called Analog Designer and running on a
Mac. The GUI is shown in the Fig. 1, below. It
allowed calculating all the important design parameters
from the inversion factor, corresponding to the
top axes in the figure. Then all the other parameters
were updated simultaneously when sweeping the first
vertical bar. The designer, hence, could then optimize
the operating point most appropriate for the particular
task of the single transistor to be sized.
EKV design methodology was extended by D. M.
Binkley beyond what was initially created, looking at
all the different design cases that may be faced. For
example, he extended the definition of the inversion
Fig. 1. The Analog Designer tool illustrating the basics of
the design methodology based on the inversion coefficient
[61].
factor to include important effects such as velocity saturation
and mobility reduction due to the vertical
field, allowing for a more accurate design for shortchannel
devices at high inversion factors. Drain
induced barrier lowering (DIBL) is also included in
the calculation of the voltage gain, since it often dominates
the channel length modulation (CLM) effect at
short transistor length and low inversion factors. D. M.
Binkley recently published a book on his work making
it the first true reference on the original EKV
design methodology and the many extensions he
developed [60].
III. LOW-POWER CIRCUIT DESIGN
The EKV MOS transistor model and the related design
methodology has been taught for many years and has
been used by many designers for the design of lowpower
circuits. Many circuits that were developped by
E. Vittoz, F. Krummenacher, our Ph.D. students and
myself, have in one way or another used and
improved the methodology.
I started to use the EKV design methodology immediately
after my Ph.D., when, together with F. Krummenacher
(the “K” of EKV) we founded Smart Silicon
Systems in 1989. We were working together with Erik
Heijne and other teams at CERN developing several
CMOS strip and pixel detector front-end read-out
chips 3 [62]-[65]. After I joined the Electronics Labs at
EPFL in 1992, apart from the modeling work mentioned
above, my other Ph.D. students were working
on low-power and low-voltage CMOS design and
were intensively using the EKV design methodology.
With the purpose of having ever decreasing supply
voltages, the concept of log-domain circuits was first
investigated. The log-domain approach uses instantaneous
companding where the currents, having basically
an unlimited dynamic range (DR), are com-
3 For more details on the history of CMOS read-out chip design for particle
physics experiment, please read the article by E. Heijne in this issue.
26 IEEE SSCS NEWS Summer 2008