4 Final Report - Emits - ESA

4 Final
Report
4.3.3.2 UV-VNIR focal planes
For UV and VNIR spectral bands (from 315 to 1040 nm), silicon semi-conductor is the only material
considered, thanks to its large maturity, its lower cost, its ability to build large format arrays and its low
dark current at ambient temperature. Monolithic CMOS array is preferred to CCD for its good maturity
to build large arrays, its better immunity to GEO harsh radiation environment (as shown by
GOCI/COMS CMOS detector qualification) and because smearing during transfer rules out large CCD
arrays for Earth observation.
Monolithic CMOS imagers manufactured with processes optimised for imaging applications (so-called
“CIS”) look by far as the most promising technology for Geo-Oculus. Indeed, thanks to improved
photodiode processes, CIS arrays are featuring excellent electro-optics performances even for small
pixel pitches. Thinned backside CMOS technology is considered to improve the fill factor and therefore
the detection efficiency. Back-illuminated CMOS are already available in the USA and are being
investigated in Europe, so availability in a 5-year frame is very likely.
Considering only mandatory channels, the spectral range to be covered by the CMOS detector (0.4
0.9 µm) is compatible with a conventional “broadband” detector. When accounting for optional
channels, it is impossible to have a good detection efficiency in the large spectral range to be covered
by the CMOS detector (0.315 to 1.04 µm), so two detectors are used, one optimised for UV & short
visible wavelengths (“UV-blue” detector) and the other for red & NIR wavelength (“Red-NIR” detector).
The largest space CMOS arrays currently available in Europe are in the range of 1.5k x 1.5k pixels
(e.g. COBRA2M 2 Mpixels detector developed by Astrium & ISAE/CIMI for the COMS/GOCI
instrument). The next step will be 3k x 3k arrays, expected for 2010-2011. There is therefore a major
step to be performed in order to reach the typical 100 Mpixel array size required for Geo-Oculus. Even
though there is no strict limitation in CMOS array size, such large arrays set many technical
challenges. In particular, the manufacturing process shall be well mastered to guaranty a sufficient
yield, i.e. a reasonable cost & development schedule. Moreover, to build a very large format array
without dead zone with good electro-optics performances and not to constraint too much the planarity,
stitching (i.e. gap-less array assembly during manufacturing process) will be required (see Figure
4.3-7) since the total array will not fit within the stepper field (currently limited to 22x22 mm²).
– Sub-blocks are exposed one after
another
– Some blocks are used multiple
times
– Ultimate limit is given by wafer size
22mm
V
1
Stepper field
horiscan2
horiscan1
V V
2 3
array
Stitched CMOS Sensor
horiscan1 horiscan2
array array array
array array array
array array array
Figure 4.3-7: Wafer-level stitching is used to build arrays with size larger than the stepper field
As for the 2 Mpixels detector of the GOCI instrument, it is proposed that the array is divided 4 subblocks
independently operated, offering a redundancy level in case of failure (see Figure 4.3-8). Each
Page 4-34 Doc. No: GOC-ASG-RP-002
Issue: 2
Astrium GmbH Date: 13.05.2009
V
1
V
2
V
3