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Lecture Notes in Computer Science 3472

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18 Run-Time Verification 537<br />

(propositions are represented by nodes), if the result is true then the BTT-FSM<br />

stays <strong>in</strong> state s1 else is off is evaluated; if is off is false then the BTT-FSM<br />

stays <strong>in</strong> state s1 else is clos<strong>in</strong>g is evaluated; if is clos<strong>in</strong>g is true then the output<br />

is “formula violated” else the BTT-FSM moves to state s2. Whenaterm<strong>in</strong>al<br />

event is received due to term<strong>in</strong>ation of monitor<strong>in</strong>g, if the BTT-FSM is <strong>in</strong> state<br />

s1 then is flash<strong>in</strong>g is evaluated; if is flash<strong>in</strong>g is true then true is returned,<br />

else is off is evaluated; if is off is true, false is returned, otherwise is true<br />

is returned. S<strong>in</strong>ce only true/false messages are reported on term<strong>in</strong>al events, the<br />

BTT-FSM that is executed when a term<strong>in</strong>al event is recognized is a B<strong>in</strong>ary<br />

Decision Diagram.<br />

gate=open<br />

light = off<br />

open<br />

gate=open off<br />

light = off<br />

gate=open clos<strong>in</strong>g gate=clos<strong>in</strong>g<br />

light = off<br />

light = off<br />

s2 s2 s2 false<br />

Fig. 18.5. Evaluation of the trace open, off, clos<strong>in</strong>g, flash<strong>in</strong>g<br />

In our example, at the <strong>in</strong>itial state the gate is open and the light is off.<br />

Figure 18.5 and 18.6 show the detailed evaluation progress for the traces:<br />

• open, off, clos<strong>in</strong>g, flash<strong>in</strong>g. (Formula violated)<br />

• open, off, flash<strong>in</strong>g, clos<strong>in</strong>g. (Formula verified)<br />

gate = open open gate = open off<br />

light = off light = off<br />

s2 s2 s2<br />

gate = open flash<strong>in</strong>g gate = open clos<strong>in</strong>g<br />

light = off<br />

light = flash<strong>in</strong>g<br />

gate = clos<strong>in</strong>g<br />

light = flash<strong>in</strong>g<br />

s1 true<br />

Fig. 18.6. Evaluation of the trace open, off, flash<strong>in</strong>g, clos<strong>in</strong>g<br />

To simplify evaluation of the propositions <strong>in</strong> the BTT-FSM’s nodes, the value<br />

assumed from the abstract state variables at each step is reported <strong>in</strong> the diagram.<br />

The identifier of states traversed dur<strong>in</strong>g the evaluation process and eventually<br />

the verdict are shown below state variables. A transition from a state to the<br />

follow<strong>in</strong>g one is performed by evaluat<strong>in</strong>g an event of the execution trace. Events<br />

that are successively evaluated are reported as labels of the edges. For example,<br />

<strong>in</strong> the case of the sequence <strong>in</strong> Figure 18.5, the <strong>in</strong>itial state of the BTT-FSM<br />

is obta<strong>in</strong>ed by apply<strong>in</strong>g the <strong>in</strong>itial state of the system to state s1. The light is<br />

<strong>in</strong>itially off, therefore the value of is flash<strong>in</strong>g is false and the value of is off<br />

is true; moreover, the gate is open, thus is clos<strong>in</strong>g is false, therefore the BTT-<br />

FSM evolves to state s2. Then the event open is considered and the BTT-FSM<br />

is evaluated aga<strong>in</strong>. Now, we are <strong>in</strong> state s2 and both is flash<strong>in</strong>g and is clos<strong>in</strong>g<br />

are false, hence we rema<strong>in</strong> on state s2. The evaluation procedure cont<strong>in</strong>ues <strong>in</strong><br />

this way until the event clos<strong>in</strong>g is reached. In this example, the BTT-FSM gets<br />

the non-term<strong>in</strong>al event clos<strong>in</strong>g while it is <strong>in</strong> state s2, with the light set on off

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