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Lecture Notes in Computer Science 3472

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90 Angelo Gargant<strong>in</strong>i<br />

b/1<br />

a/0<br />

s1<br />

b/1<br />

a/1 s2 s3 a/0<br />

b/1<br />

MI 1<br />

a/0<br />

b/0<br />

s1<br />

a/0<br />

b/1 s2 s3 b/1<br />

a/1<br />

MI 2<br />

Fig. 4.2. Two faulty implementations of MS<br />

<strong>in</strong> its <strong>in</strong>itial state we can apply a hom<strong>in</strong>g sequence (presented <strong>in</strong> Section<br />

1.1.3) and then start the conformance test. If the mach<strong>in</strong>e MI does not<br />

conform to its specification and the hom<strong>in</strong>g sequence fails to br<strong>in</strong>g MI to its<br />

<strong>in</strong>itial state, this will be discovered dur<strong>in</strong>g the conformance test. We denote<br />

the <strong>in</strong>itial state by s1.<br />

(6) Same number of states: MI has the same number of states as MS , hence<br />

faults do not <strong>in</strong>crease the number of states. Due to this assumption, the<br />

possible faults <strong>in</strong> MI are of two k<strong>in</strong>ds: output faults, i.e. a transition <strong>in</strong><br />

the implementation produces the wrong output, and transfer faults, i.e. the<br />

implementation goes to a wrong state. Figure 4.2 shows two faulty implementations<br />

of the specification mach<strong>in</strong>e MS given <strong>in</strong> Figure 4.1. Mach<strong>in</strong>e<br />

MI 1 conta<strong>in</strong>s only one output fault for the transition from s3 to s1 with the<br />

<strong>in</strong>put b: the output produced by MI 1 is 1 <strong>in</strong>stead of 0. Mach<strong>in</strong>e MI 2 has<br />

several transfer faults: every transition moves the mach<strong>in</strong>e to a wrong f<strong>in</strong>al<br />

state. Moreover the transitions <strong>in</strong> MI 2 from state s3 and s1 with <strong>in</strong>put b<br />

produce wrong outputs.<br />

Although this assumption is very strong, we show <strong>in</strong> Section 4.7 that many<br />

methods we present work well with modifications under the more general<br />

assumption that the number of states of MI is bounded by an <strong>in</strong>teger m,<br />

which may be larger than the number of states n <strong>in</strong> MS .<br />

(7) reset message: MI and MS have a particular <strong>in</strong>put reset (or briefly r) that<br />

from any state of the mach<strong>in</strong>e causes a transition which ends <strong>in</strong> the <strong>in</strong>itial<br />

state s1 and produces no output. Formally, for all s ∈ S, δ(s, reset )=s1 and<br />

λ(s, reset )=−. Start<strong>in</strong>g from Section 4.5 we present some methods that do<br />

not need a reset message.<br />

(8) status message: MI and MS have a particular <strong>in</strong>put status and they respond<br />

to a status message with an output message that uniquely identifies their<br />

current state. S<strong>in</strong>ce we label the states s1, s2, ..., sn, weassumethatstatus<br />

outputs the <strong>in</strong>dex i when applied to state si. The mach<strong>in</strong>es do not change

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