Tutorial als PDF - CES

Kapitel 7
Anhang
7.1 VHDL-Code für GGT
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-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 10.1.02
-- \ \ Application :
-- / / Filename : xil_F6mGuc
-- /___/ /\ Timestamp : 10/21/2008 13:23:54
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity GGT is
port ( CLK : in std_logic;
IN1 : in std_logic_vector (7 downto 0);
IN2 : in std_logic_vector (7 downto 0);
RESET : in std_logic;
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