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MODE : BUFFER std_logic;
RESET : BUFFER std_logic;
VALUE1 : BUFFER std_logic_vector (7 downto 0);
VALUE2 : BUFFER std_logic_vector (7 downto 0);
DATA : inout std_logic_vector (7 downto 0));
end USB_INTERFACE;
architecture BEHAVIORAL of USB_INTERFACE is
signal Out_data : Std_Logic_Vector(7 downto 0); -- Zwischenlager für Ausgang
BEGIN
output_selection : process(adr, value1, value2, comp_value, reset, mode)
begin
case adr is
when "00" => Out_data Out_data Out_data Out_data mode, 1 => reset, others => ’0’);
when others => Out_data ’0’);
end case;
end process;
write_process : process(adr, wr_n)
begin
if wr_n = ’1’ and wr_n’event then
case adr is
when "00" => value1 value2 Comp_Value mode