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7.2 VHDL-Code für COMPARATOR
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-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 10.1.02
-- \ \ Application :
-- / / Filename : xil_GcbZlx
-- /___/ /\ Timestamp : 10/21/2008 13:24:02
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity COMPARATOR is
port ( IN1 : in std_logic_vector (7 downto 0);
IN2 : in std_logic_vector (7 downto 0);
EQUAL : out std_logic);
end COMPARATOR;
architecture BEHAVIORAL of COMPARATOR is
begin
COMPARE: process(IN1, IN2)
begin
if IN1 = IN2 then
EQUAL