Xcell Journal Issue 78: Charge to Market with Xilinx 7 Series ...

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XPLANATION: FPGA 101 IMPLEMENTING DIFFERENT FILTER TOPOLOGIES No matter what the end type of filter— bandpass, band reject or high pass— all of these start out with the initial design of a low-pass filter. If you know how to create a low-pass filter and a high-pass filter, you can then use combinations of the two to produce bandreject and bandpass filters. Let’s first examine how to convert a low-pass filter into a high-pass one. The simplest method, called spectral inversion, changes the stopband into the passband and vice versa. You perform spectral inversion by inverting each of the samples while at the same time adding one to the center sample. The second method of converting to a high-pass filter is spectral reversal, which mirrors the frequency response; to perform this operation, simply invert every other coefficient. Having designed the low- and highpass filters, it’s easy to make combinations that you can use to generate bandpass and band-reject filters. To generate a band-reject filter, just place a high-pass and a low-pass filter in parallel with each other and sum together the outputs. You can assemble a bandpass filter, meanwhile, by placing a low-pass and a high-pass filter in series with each other. AND NOW FOR THE DESIGN The information we’ve reviewed so far details what windowed-sinc filters are, the importance of windowing and how to generate filters of different topologies. However, before you can implement your filter within an FPGA, you must generate a set of filter coefficients using one of several software tools, such as Octave, MATLAB ® or even Excel. Many of these tools provide simplified interfaces and options, allowing you to design the filter with Figure 5 – Xilinx CORE Generator frequency responses: Top, truncated sinc (left) and Blackman window. Bottom, Hamming window (left) and Hamming-windowed high-pass filter 40 Xcell Journal First Quarter 2012
Digital filters find their way into many applications these days, and FPGAs offer a significant advantage to the system designer who needs to use them. minimal effort, the FDA tool in MAT- LAB being a prime example. Having generated a set of coefficients for the desired filter, you are ready to implement your filter within the FPGA. No matter the number of taps you have decided on, the basic structure of each stage of the FIR filter will be the same and will consist of a multiplier, storage and adder. The method most engineers prefer, and the one that’s by far the simplest, is to use the Xilinx ® CORE Generator tool’s FIR Compiler, which provides multiple options for customizing and for generating advanced filters. You can import the generated coefficients into the FIR Compiler as a COE file; this file will contain the coefficients for the filter with the radix also being declared. Radix=10; Coefdata = -0.013987944, -0.01735736, -0.005971498, 0.012068368, 0.02190073, Once you have loaded these coefficients, FIR Compiler will display the frequency response of the filter for the coefficients provided, along with basic performance characteristics such as stopband attenuation and passband ripple. Once you have completed your customization of the filter using the FIR Compiler tool, CORE Generator will produce all the necessary files to both implement the design and to simulate it during behavioral simulation prior to implementation, provided the user has access to the correct simulation libraries. If you prefer, you can also implement the filter in HDL you have generated yourself. This will often be the choice if your final implementation will be in an ASIC and you are using the FPGA implementation as a prototyping system. In this case, the first step is to quantize the filter coefficients to use a fixed-number representation of the floating-point results. As the filter coefficients will represent positive and negative numbers, it is common practice to represent these in a two’s complement format. Once these coefficients have been quantized, you can use them as constants within the HDL design. Digital filters find their way into many applications these days, and FPGAs offer a significant advantage to the system designer who needs to use them. Windowed-sinc filters are very simple to design and implement using basic math tools along with either FPGA core-generation tools or directly in HDL. XPLANATION: FPGA 101 First Quarter 2012 Xcell Journal 41
Page 1 and 2: Xcell ISSUE 78, FIRST QUARTER 2012
Page 3 and 4: Add it up: 10 GbE, 40 GbE, and 100G
Page 6 and 7: C O N T E N T S VIEWPOINTS XCELLENC
Page 8 and 9: COVER STORY Charge to Market with X
Page 10 and 11: COVER STORY CUSTOMER INNOVATION hav
Page 12 and 13: COVER STORY The ROHS-compliant Kint
Page 14 and 15: XPERT OPINION Embedded Vision: FPGA
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Page 20 and 21: XCELLENCE IN AUTOMOTIVE APPLICATION
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Page 48 and 49: XPLANATION: FPGA 101 Tips and Trick
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Page 52 and 53: ASK FAE-X How to Build a Self-Check
Page 54 and 55: ASK FAE-X Disk File Stimulus Script
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