Xcell Journal Issue 78: Charge to Market with Xilinx 7 Series ...

A very simple synchronous switchedmode
DC/DC converter consists of a
pair of MOSFET switches, an inductor,
and input and output filter capacitors.
Figure 1 shows the converter during the
switching cycle and its associated DC
and AC current paths. When SW1 is
closed (SW2 open), current flows from
the source though the inductor and to
the load, while the input and output filter
capacitors “shunt” the high-frequency
AC currents. When SW2 is closed
(SW1 open), energy stored in the inductor
sources the current to the load
SW1
through the second half of the switching
cycle. The opening and closing of these
switches and flow of the high-frequency
AC currents create noise.
NOISE AND STRATEGIES
FOR ITS MITIGATION
A stepdown DC/DC converter effectively
“chops up” a DC voltage into an
AC voltage and then filters it back to a
pseudo-DC voltage. This process introduces
noise of four types: ripple voltage
on the converter DC output, ripple
voltage on the converter input supply,
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radiated electromagnetic interference
and conducted EMI.
Every passive electrical component
has, besides its basic function (resistance,
capacitance, inductance), a parasitic
component of the other two: an
equivalent series resistance (ESR)
and an equivalent series inductance
(ESL), in the case of a capacitor. For a
resistor, an equivalent series inductance
and an equivalent parallel
capacitance are present as well.
Output ripple is the byproduct of
the shunting off, or flow, of the AC
ripple current through the output filter
capacitor. Figure 2 shows the
small-signal model of the output filter
capacitor and the contribution of
each element of the model to the output
ripple waveform. Note that the
ESL of the output filter capacitor
combines with the parasitic inductance
of the PCB traces’ return, and
the internal parasitic inductance of
the converter, to create the total ESL
of the output filter loop. The ESL creates
the large high-frequency spikes
through inductive “ringing.”
Most DC/DC converter supplier
datasheets show low-pass-filtered ripple
waveforms and are thus generally
unreliable as an indication of the actual
ripple that would be measured on
the PCB for a given application.
Fundamentally, to reduce output ripple
you can either reduce the magnitude
of the ripple current, or reduce the ESR
and ESL of the capacitor and the ESL of
the PCB traces. Operating at higher
switching frequencies will reduce the
ripple current for a given inductor value
and allows you to use smaller, low-
ESR/ESL ceramic capacitors. However,
a higher switching frequency increases
switching losses in the MOSFET switches
and will affect efficiency.
Placing multiple capacitors in parallel
can reduce ESR/ESL in the same
way that placing resistors in parallel
reduces their combined resistance. But
adding capacitors increases ESL in the
PCB and and will increase the PCB
real estate the converter consumes.
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Figure 1 – In this simplified diagram of a synchronous stepdown DC/DC converter,
the solid red line shows the flow of DC currents while the dotted red line
shows the flow of high-frequency AC current.
Output Ripple Waveform Capacitor Equivalent Circuit
Figure 2 – Output voltage ripple components and sources
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