Xcell Journal Issue 78: Charge to Market with Xilinx 7 Series ...

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XPLANATION: FPGA 101 Tips and Tricks for Better Floating-Point Calculations in Embedded Systems Floating-point arithmetic does not play by the rules of integer arithmetic. Yet, it’s not hard to design accurate floating-point systems using FPGAs or FPGA-based embedded processors. by Sharad Sinha PhD Candidate Nanyang Technological University, Singapore sharad_sinha@pmail.ntu.edu.sg Engineers tend to shy away from floating-point calculations, knowing that they are slow in software and resource-intensive when implemented in hardware. The best way to understand and appreciate floating-point numbers is to view them as approximations of real numbers. In fact, that is what the floating-point representation was developed for. The real world is analog, as the old saying goes, and many electronic systems interact with real-world signals. It is therefore essential for engineers who design those systems to understand the strength as well as the limitations of floating-point representations and calculations. It will help us in designing more reliable and error-tolerant systems. 48 Xcell Journal First Quarter 2012
Let’s take a closer look at floating-point arithmetic in some detail. Some example calculations will establish the fact that floating-point arithmetic is not as straightforward as integer arithmetic, and that engineers must take this into account when designing systems that operate on floating-point data. One important technique can help: using a logarithm to operate on very small floating-point data. The idea is to gain familiarity with a few flavors of numerical computation and focus on design issues. Some of the references at the end of this article will offer greater insight. As for implementation, designers can use Xilinx ® LogiCORE IP Floating-Point Operator to generate and instantiate floating-point operators in RTL designs. If you are building floating-point software systems using embedded processors in FPGAs, then you can use the LogicCORE IP Virtex ® -5 Auxiliary Processor Unit (APU) Floating Point Unit (FPU) for the PowerPC 440 embedded processor in the Virtex-5 FXT. FLOATING-POINT ARITHMETIC 101 IEEE 754-2008 is the current IEEE standard for floatingpoint arithmetic. (1) It overrides the IEEE 754-1985 and IEEE 754-1987 versions of the standard. The floating-point data represented in the standard are: ■ Signed zero: +0, -0 ■ Nonzero floating-point numbers represented as (-1)^s x b^e x m where: s is +1 or -1, thus signifying whether the number is positive or negative, b is a base (2 or 10), e is an exponent and m is a number of the form d0.d1d2-------dp-1, where di is either 0 or 1 for base 2 and can take any value between 0 and 9 for base 10. Note that the decimal point is located immediately after d0. ■ Signed infinity: +∞ , -∞ ■ Not a number (NaN) includes two variants: qNaN (quiet) and sNaN (signaling) The term d0.d1d2-------dp-1 is called the “significand” and e is called “exponent.” The significand has “p” digits where p is the precision of the representation. IEEE 754-2008 defines five basic representation formats, three in base 2 and two in base 10. Extended formats are also available in the standard. The single-precision and double-precision floating-point numbers in IEEE 754-1985 are now referred to as binary32 and binary64 respectively. For every format, there is the smallest exponent, emin, and the largest exponent, emax. The possible range of finite values that can be represented in a format is determined by the base (b), precision (p) and emax. The standard defines emin as always equal to 1-emax: ■ m is an integer in the range 0 to b^p-1. For example, for p = 10 and b = 2, m is from 0 to 1023. ■ e, for a given number, must satisfy 1-emax
Page 1 and 2: Xcell ISSUE 78, FIRST QUARTER 2012
Page 3 and 4: Add it up: 10 GbE, 40 GbE, and 100G
Page 6 and 7: C O N T E N T S VIEWPOINTS XCELLENC
Page 8 and 9: COVER STORY Charge to Market with X
Page 10 and 11: COVER STORY CUSTOMER INNOVATION hav
Page 12 and 13: COVER STORY The ROHS-compliant Kint
Page 14 and 15: XPERT OPINION Embedded Vision: FPGA
Page 16 and 17: XPERT OPINION Ethernet interface. T
Page 18 and 19: XPERT OPINION Figure 3 - Pedestrian
Page 20 and 21: XCELLENCE IN AUTOMOTIVE APPLICATION
Page 32 and 33: XCELLENCE IN PROTOTYPING Lowering t
Page 34 and 35: XCELLENCE IN PROTOTYPING 3.3 GPIO V
Page 36 and 37: XPLANATION: FPGA 101 Ins and Outs o
Page 38 and 39: XPLANATION: FPGA 101 Figure 2 - IDF
Page 40 and 41: XPLANATION: FPGA 101 IMPLEMENTING D
Page 42 and 43: XPLANATION: FPGA 101 Using FPGAs to
Page 44 and 45: XPLANATION: FPGA 101 FIR filter imp
Page 46 and 47: XPLANATION: FPGA 101 S n 12 K0 0 DS
Page 50 and 51: XPLANATION: FPGA 101 Parameter Bina
Page 52 and 53: ASK FAE-X How to Build a Self-Check
Page 54 and 55: ASK FAE-X Disk File Stimulus Script
Page 56: ASK FAE-X either the simulator cons
Page 59 and 60: A very simple synchronous switchedm
Page 61: from the input voltage rail, which
Page 65 and 66: Revision highlights: All ISE Design
Page 68: Twice the performance. Half the pow

Xcell Journal Issue 78: Charge to Market with Xilinx 7 Series ...

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