BLOCKING READER: DESIGN AND IMPLEMENTATION OF A ...

5.3.5 Single processor transceiver design
This Single processor transceiver design as shown in the Figure 5.6 can be said
as a simplest design. In this design there is a powerful PIC memory sufficient to
hold the protocol. A Transceiver that does both transmit and receive of RF signals.
The choice of a transceiver IC is very important for this design. And should be
able to comply on all the parameters discussed earlier. Again the processor used
here should be a 16-bit micro-controller to handle the transceiver. We also note that
there is no need for the circulator in this design as the transceiver can do half duplex
communication. There is no problem of isolation in this circuit as the design has one
antenna.
One disadvantages of this design is it can mostly be used in low power appli-
cations, hence the range decreases. A passive RFID Tag uses power from the reader
for communication so it is required for the Reader to switch between transmit and
receive quickly. The power constraints can be over come by a simple amplifier circuit.
On research and careful consideration this architecture is considered for the
design of the Passive UHF RFID Reader in this paper. Important reasons being the
simplest design and low cost.
Let us see how the Single processor transceiver design can comply on the design
constraints. Cost of the total design should not exceed 30$. The cost discretion is as
shown in the Table 5.5 below. From the table we can see that the cost is complied
with less that 30$. The next constraint was to see if the design could comply on
the Gen2 protocol. Here the transceiver and the RF circuit used should be able to
comply on the protocol. CC1101 is the transceiver used in this design this IC is
design by Chip Con. The description of the IC CC1101 is as mentioned below. On
research this IC was considered as a better option for this design. The next constraint
was the on supporting read/write of the tags. This shouldnt be a problem with the
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