BLOCKING READER: DESIGN AND IMPLEMENTATION OF A ...

6.1 Introduction
CHAPTER 6
IMPLEMENTATION
The Blocking Reader uses the Reader design shown in Figure 5.6. This looks
like a simple design but implementation of this requires proper selection of the IC’s
that satisfies the basic requirements.
6.2 Circuit Diagram
6.2.1 Processor
The processor used in this design is C8051F320. The processor is having a
16Kbytes of Flash sufficient to program a Blocking Reader. It supports all USB and
UART modes which provides interface to the server. 25/21 digital I/O ports and 16-
bit programmable counter array which can be used to interface with the transceiver.
The processor is high speed with pipelined instruction architecture executing 70% of
instructions in 1 or 2 clock cycles provides a fast programming of transceiver IC. It
is having a throughput of 25MIPS with a clock of 25MHz. It comes in the packaging
of 32-pin LQFP. The µController connections are as shown in the Figure 6.6.
6.2.1.1 Programming
The 8051µC chip include on-chip Silicon Labs 2-Wire (C2) debug circuitry. It
allows a non-intrusive, full speed, in-circuit debugging. A full access to 16KB flash,
2304 bytes of on chip memory and registers. Debugging logic supports setting break
point, single stepping, run and halt commands. The thesis use a Keil µVision 3 for
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