Performance Analysis and Optimization of the Hurricane File System ...

CHAPTER 4. EXPERIMENTAL SETUP 33
memory results is shown in Figure 4.3. These results demonstrate that the perfect memory model eliminated
memory bank access time, bus access time, and cache coherency overhead.
4.7.2 Memory System Saturation
The SimOS memory system parameters are given in Table 4.1. For instance: 177 MB/s bus bandwidth,
1 memory bank, and 2100 ns memory access time are critical memory parameters. However, these parameters
alone do not describe memory system behavior under increasing contention. We ran a simple experiment
to depict the characteristics and limitations of the memory system. File system scalability is limited to the
maximal throughput of these hardware components. In the experiment, each processor executes a thread
that sequentially traverses a separate, independent 2 MB array, reading and modifying each array element.
The nature of the modification is a simple increment of the current value in the array element. Each element
is 1 byte in size. The array is allocated local to each processor, using K42’s memory allocation routines. The
allocation performs padding at the array boundaries to prevent false sharing of cache lines. The 2 MB array
size ensured the data set would not fit in the 1 MB secondary cache so that read and write accesses to main
memory were necessary. The goal of the experiment was to saturate the bus or the sole memory bank with
memory traffic from the array accesses to determine the maximum load that can be placed on the system.
Figure 4.4 shows that performance was satisfactory for up to 4 processors but degraded drastically
beyond this point. Under continuous, intense pressure, the bus or memory bank could adequately service a
maximum of 4 processors. In practice, this worst-case scenario should rarely occur since the processor caches
should reduce the amount of memory bus traffic.