03.08.2013 Views

Embedded Software and Motor Control Libraries for PXR40xx

Embedded Software and Motor Control Libraries for PXR40xx

Embedded Software and Motor Control Libraries for PXR40xx

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

A general <strong>for</strong>m of the IIR filter expressed as a transfer function in the Z-domain is<br />

described as follows:<br />

Equation GDFLIB_FilterIIR1_Eq1<br />

where N denotes the filter order. The first order IIR filter in the Z-domain is there<strong>for</strong>e<br />

given from equation GDFLIB_FilterIIR1_Eq1 as:<br />

Equation GDFLIB_FilterIIR1_Eq2<br />

In order to implement the first order IIR filter on a microcontroller, the discrete time<br />

domain representation of the filter, described by equation GDFLIB_FilterIIR1_Eq2, must<br />

be trans<strong>for</strong>med into a time difference equation as follows:<br />

Equation GDFLIB_FilterIIR1_Eq3<br />

Chapter 4 API References<br />

where: x[k] is the input signal, y[k] is the output signal, a i <strong>and</strong> b i are the filter<br />

coefficients. Equation GDFLIB_FilterIIR1_Eq3 represents a Direct Form I<br />

implementation of a first order IIR filter. It is well known that Direct Form I (DF-I) <strong>and</strong><br />

Direct Form II (DF-II) implementations of an IIR filter are generally sensitive to<br />

parameter quantization if a finite precision arithmetic is considered. This, however, can<br />

be neglected when the filter transfer function is broken down into lower order sections,<br />

i.e. first or second order. The main difference between DF-I <strong>and</strong> DF-II implementations<br />

of an IIR filter is in the number of delay buffers <strong>and</strong> in the number of guard bits required<br />

to h<strong>and</strong>le the potential overflow. The DF-II implementation requires less delay buffers<br />

than DF-I, hence less data memory is utilized. On the other h<strong>and</strong>, since the poles come<br />

first in the DF-II realization, the signal entering the state delay-line typically requires a<br />

larger dynamic range than the output signal y(k). There<strong>for</strong>e, overflow can occur at the<br />

delay-line input of the DF-II implementation, unlike in the DF-I implementation.<br />

Because there are two delay buffers necessary <strong>for</strong> both DF-I <strong>and</strong> DF-II implementation of<br />

the first order IIR filter, the DF-I implementation was chosen to be used in the<br />

GDFLIB_FilterIIR1_FLT function.<br />

<strong>Embedded</strong> <strong>Software</strong> <strong>and</strong> <strong>Motor</strong> <strong>Control</strong> <strong>Libraries</strong> <strong>for</strong> <strong>PXR40xx</strong>, Rev. 1.0<br />

Freescale Semiconductor, Inc. 179

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!