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TM<br />
Correctable<br />
• Correctable Error Status Register<br />
− provides additional information for 6 correctable errors<br />
− Correctable error status bit is set independent of the Mask Register<br />
setting!<br />
• Correctable Error Mask Register<br />
− provides 6 correctable error mask bits to let device control whether to<br />
mask or unmask a particular correctable error condition to be reported<br />
to RC<br />
− A masked error:<br />
is not logged in the Header Log Register<br />
is not reported to the RC by device<br />
Only affects the error reporting, not the status bits!<br />
27<br />
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,<br />
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,<br />
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,<br />
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All<br />
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.