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• The UR is a PCIe Uncorrectable Non-Fatal Error! • Who is mainly responsible for detecting & reporting UR Error? − The base specification places the burden on the Completer! The recipient of the original request is responsible! Or, the one decides to treat a request as UR is responsible for reporting error! • The original Requester has minimum information for an UR Error Requester Root Complex or Switch TM UR Completion TLP MRd Request 38 TLP Completer End point Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• The scenario is: as a Completer, − It receives a Unsupported Request TLP from the original transaction Requester (or Initiator) − It can send an ERR_FATAL or ERR_NONFATAL Error Message (depending on severity setting) toward RC, if error reporting is enabled with either Command Register [SERR_EN] or Device Control Register [URR and FER or NFER], regardless the TLP type − It may return a Completion with UR status if the UR TLP type is Non-Posted Requester Completer Root Complex or Switch TM UR Completion TLP MRd Request ERR_x Message TLP PCIe Error Message 39 I am here! I am going to treat you as UR! End point Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Page 1 and 2: August 2012 TM Freescale, the Frees
Page 3 and 4: • Brief Overview of PCI Express A
Page 7 and 8: TM Links Root Complex Device Switch
Page 9 and 10: • Packet-based split-transaction
Page 13 and 14: Error Error Detection TM Error Logg
Page 15 and 16: TM 15 Freescale, the Freescale logo
Page 17 and 18: • Example 1: 1) Sender sends a TL
Page 19 and 20: • Characteristics of Uncorrectabl
Page 21 and 22: Poisoned TLP Rcvd, ECRC Error, Unsu
Page 23 and 24: TM 23 EP Mode Freescale, the Freesc
Page 25 and 26: • Finer granularity in defining t
Page 27 and 28: TM Correctable • Correctable Erro
Page 31 and 32: Byte 0 Byte 4 Byte 8 Byte 12 TM 31
Page 33 and 34: 2 6 5 4 e500mc Core Completion Queu
Page 37: • Why is a Request TLP treated as
Page 41 and 42: • The scenario is: as a Requester
Page 45 and 46: • The Completion Timeout is a PCI
Page 49 and 50: PEX3 Error PEX2 Error PEX1 Error In
Page 51 and 52: 5 4 3 e500mc Core 7 e500mc Core 0 1
Page 53 and 54: FMAN0 Error MPIC core 0 mcp asserti
Page 55 and 56: • What does it mean for full regi
Page 57 and 58: • PCI Express is a complicated hi
Page 59 and 60: • Books: - PCI System Architectur

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