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• Brief Overview of PCI Express Architecture and Protocol • Introduction to PCI Express Errors − Error Classification, Detection, Logging, Signaling • PCI Express Uncorrectable Errors impacting system stability • PCI Express Uncorrectable Error Case Study - UR − UR Error Definition and Clarification − UR Cause, Detection and Logging • PCI Express Uncorrectable Error Case Study – Completion Timeout − CTO Error Definition and Clarification − CTO Cause, Detection and Logging • P4080 SoC Platform and PCIe Error Interrupt Generation Path • PCI Express Outbound MRd/UR Completion Error Handling • Summary • Reference TM 32 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
2 6 5 4 e500mc Core Completion Queue 7 Internal Completion w/bad data UR Cpl CoreNet PCIe Root Complex 1 Load Instruction Load Queue PCIe Endpoint TM 3 MRd P4080 1. P4080 host software issues a load instruction via core targeting a PCI Express downstream EP 2. The load instruction is decoded and dispatched to issue queue. It will then be tracked at completion queue. 3. The load instruction is converted to an outbound MRd transaction and passed down through CoreNet, OCN, PCI Express RC, which will convert it into a PCI Express MRd transaction and send through link to reach the downstream EP. 4. The downstream EP for some reason can’t handle the MRd. It then returns a Completion TLP w/status as “Unsupported <strong>Request</strong>”. 5. PCI Express RC terminates this MRd transaction locally and return the status marked as “bad data”. 6. Core noticed the result of this transaction marked with “bad data”. Meanwhile, the load instruction reaches the bottom of the completion queue, which expects correct return data before it can complete/finish the instruction. 7. The core can’t complete this load instruction normally!!! 33 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Page 1 and 2: August 2012 TM Freescale, the Frees
Page 3 and 4: • Brief Overview of PCI Express A
Page 7 and 8: TM Links Root Complex Device Switch
Page 9 and 10: • Packet-based split-transaction
Page 13 and 14: Error Error Detection TM Error Logg
Page 15 and 16: TM 15 Freescale, the Freescale logo
Page 17 and 18: • Example 1: 1) Sender sends a TL
Page 19 and 20: • Characteristics of Uncorrectabl
Page 21 and 22: Poisoned TLP Rcvd, ECRC Error, Unsu
Page 23 and 24: TM 23 EP Mode Freescale, the Freesc
Page 25 and 26: • Finer granularity in defining t
Page 27 and 28: TM Correctable • Correctable Erro
Page 31: Byte 0 Byte 4 Byte 8 Byte 12 TM 31
Page 37 and 38: • Why is a Request TLP treated as
Page 39 and 40: • The scenario is: as a Completer
Page 41 and 42: • The scenario is: as a Requester
Page 45 and 46: • The Completion Timeout is a PCI
Page 49 and 50: PEX3 Error PEX2 Error PEX1 Error In
Page 51 and 52: 5 4 3 e500mc Core 7 e500mc Core 0 1
Page 53 and 54: FMAN0 Error MPIC core 0 mcp asserti
Page 55 and 56: • What does it mean for full regi
Page 57 and 58: • PCI Express is a complicated hi
Page 59 and 60: • Books: - PCI System Architectur

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