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• Link – Collection of two ports and their interconnecting lanes • Lane – A set of differential signal pairs: one pair for Tx and another for Rx. • Port – Physically, a group of transmitters and receivers located on the same chip that define a link – Logically, an interface between a component and a PCI Express Link • x1, x2, x4, x8, x16, ….. xN (Link) – A by-N link is composed of N lanes TM 8 Lane 0 Channel (P-N Pair) TX0 P N P N RX0 RX0 P N P N TX0 Upstream Device Link Downstream Device TXn P N RXn P N P N P N RXn TXn Downstream Port Lane n Upstream Port Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• Packet-based split-transaction protocol • Provides R/W logical transactions to software • 4 basic transaction types: memory, I/O, configuration and message • 32-bit and 64-bit memory addressing • Three routing methods – Address routing (memory and I/O) – ID routing (configuration) – Implicit routing (messages) • Transactions are carried by Transaction Layer Packets (TLPs) Root Complex or Switch TM Ack Req D DLLP FC Update DLLP Req 4 TLP Req C TLP Ack Req C DLLP Ack Req 3 DLLP 9 Req 3 TLP Req D TLP FC Update DLLP Ack Req 4 DLLP End point Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Page 1 and 2: August 2012 TM Freescale, the Frees
Page 3 and 4: • Brief Overview of PCI Express A
Page 7: TM Links Root Complex Device Switch
Page 13 and 14: Error Error Detection TM Error Logg
Page 15 and 16: TM 15 Freescale, the Freescale logo
Page 17 and 18: • Example 1: 1) Sender sends a TL
Page 19 and 20: • Characteristics of Uncorrectabl
Page 21 and 22: Poisoned TLP Rcvd, ECRC Error, Unsu
Page 23 and 24: TM 23 EP Mode Freescale, the Freesc
Page 25 and 26: • Finer granularity in defining t
Page 27 and 28: TM Correctable • Correctable Erro
Page 31 and 32: Byte 0 Byte 4 Byte 8 Byte 12 TM 31
Page 33 and 34: 2 6 5 4 e500mc Core Completion Queu
Page 37 and 38: • Why is a Request TLP treated as
Page 39 and 40: • The scenario is: as a Completer
Page 41 and 42: • The scenario is: as a Requester
Page 45 and 46: • The Completion Timeout is a PCI
Page 49 and 50: PEX3 Error PEX2 Error PEX1 Error In
Page 51 and 52: 5 4 3 e500mc Core 7 e500mc Core 0 1
Page 53 and 54: FMAN0 Error MPIC core 0 mcp asserti
Page 55 and 56: • What does it mean for full regi
Page 57 and 58: • PCI Express is a complicated hi
Page 59 and 60:
• Books: - PCI System Architectur
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