Request

• Why is a Request TLP treated as UR at Completer?
− Request type not supported
− Request does not reference address space mapped within device
− Request contains address that cannot be routed to any egress port of a bridge
or a switch (address not specified in any port’s Base & Limit Registers)
Another very common cause is that the PCIe switch’s downstream port experienced link
down due to EP’s hardware or software failure!
− A transaction targeting a device on a PCI bus but is Master Aborted after the
request was accepted by the bridge.
− A configuration access that targets an un-implemented Bus, Device or Function
results in termination of the transaction, and a completion transaction is returned
with UR status.
This is very common during PCI/PCIe device tree enumeration.
It can be safely ignored.
− Message request received with unsupported or undefined message code.
TM
37
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.