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FMAN0 Error<br />
MPIC core 0 mcp assertion<br />
Core 0 MCheck ISR w/ MCSR[MCP]=1<br />
MPIC ISR w/ MCSR1[0]=1 (read only)<br />
And EISR0[0]=1 (read only)<br />
FMAN ISR checks FM_EPI (read only)<br />
If FM_EPI[0]=1 FMAN FPM ISR<br />
If FM_EPI[8]=1 FMAN BMI ISR<br />
If FM_EPI[n]=1<br />
TM<br />
FMAN ? ISR<br />
Return to MPIC ISR, check for other MCSRn bits = 1<br />
Read FPM_EE[0:2]<br />
Satisfy error, clear error bit<br />
(write 1 to clear)<br />
Check status register<br />
Return to MCheck ISR clear MCP bit (write 1 to clear), recover<br />
52<br />
Read FMBM_IEVR[0:2]<br />
Satisfy error, clear error bit<br />
(write 1 to clear)<br />
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