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FMAN0 Error MPIC core 0 mcp assertion Core 0 MCheck ISR w/ MCSR[MCP]=1 MPIC ISR w/ MCSR1[0]=1 (read only) And EISR0[0]=1 (read only) FMAN ISR checks FM_EPI (read only) If FM_EPI[0]=1 FMAN FPM ISR If FM_EPI[8]=1 FMAN BMI ISR If FM_EPI[n]=1 TM FMAN ? ISR Return to MPIC ISR, check for other MCSRn bits = 1 Read FPM_EE[0:2] Satisfy error, clear error bit (write 1 to clear) Check status register Return to MCheck ISR clear MCP bit (write 1 to clear), recover 52 Read FMBM_IEVR[0:2] Satisfy error, clear error bit (write 1 to clear) Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
FMAN0 Error MPIC core 0 mcp assertion Core 0 MCheck ISR w/ MCSR[MCP]=1 MPIC ISR w/ MCSR1[0]=1 (read only) And EISR0[0]=1 (read only) FMAN ISR checks FM_EPI (read only) If FM_EPI[0]=1 FMAN FPM ISR If FM_EPI[8]=1 FMAN BMI ISR If FM_EPI[n]=1 TM FMAN ? ISR Return to MPIC ISR, check for other MCSRn bits = 1 Read FPM_EE[0:2] Satisfy error, clear error bit (write 1 to clear) Check status register Return to MCheck ISR clear MCP bit (write 1 to clear), recover 53 Read FMBM_IEVR[0:2] Satisfy error, clear error bit (write 1 to clear) Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Page 1 and 2: August 2012 TM Freescale, the Frees
Page 3 and 4: • Brief Overview of PCI Express A
Page 7 and 8: TM Links Root Complex Device Switch
Page 9 and 10: • Packet-based split-transaction
Page 13 and 14: Error Error Detection TM Error Logg
Page 15 and 16: TM 15 Freescale, the Freescale logo
Page 17 and 18: • Example 1: 1) Sender sends a TL
Page 19 and 20: • Characteristics of Uncorrectabl
Page 21 and 22: Poisoned TLP Rcvd, ECRC Error, Unsu
Page 23 and 24: TM 23 EP Mode Freescale, the Freesc
Page 25 and 26: • Finer granularity in defining t
Page 27 and 28: TM Correctable • Correctable Erro
Page 31 and 32: Byte 0 Byte 4 Byte 8 Byte 12 TM 31
Page 33 and 34: 2 6 5 4 e500mc Core Completion Queu
Page 37 and 38: • Why is a Request TLP treated as
Page 39 and 40: • The scenario is: as a Completer
Page 41 and 42: • The scenario is: as a Requester
Page 45 and 46: • The Completion Timeout is a PCI
Page 49 and 50: PEX3 Error PEX2 Error PEX1 Error In
Page 51: 5 4 3 e500mc Core 7 e500mc Core 0 1
Page 55 and 56: • What does it mean for full regi
Page 57 and 58: • PCI Express is a complicated hi
Page 59 and 60: • Books: - PCI System Architectur

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