Errata Sheet - Infineon

Errata Sheet
Functional Deviations
word accesses, to the top and bottom of the circular buffer. However, due to the
bug, the first access takes the transfer data size from the second part of the unaligned
load and only 16-bits of data are written. Note that the presence of an
optional IP instruction between the load and store transactions does not prevent
the problem, since the load and store transactions are back-to-back in the LS
pipeline.
Case 2
Case 2 is similar to case 1, and occurs where a load instruction using circular
addressing mode encounters the circular buffer wrap-around condition, and is
preceded in the LS pipeline by a multi-access load instruction. However, for
case 2 to be a problem it is necessary that the first access of the load instruction
encountering the circular buffer wrap-around condition (the access to the top of
the circular buffer) also encounters a conflict condition with the contents of the
CPU store buffer. Again, in this case the first access of the load instruction using
circular addressing mode may incorrectly use the transfer data size from the
second part of the multi-access load instruction. Since half-word load
instructions must be half-word aligned, and ld.a instructions must be word
aligned, they cannot trigger the circular buffer wrap-around condition. As such,
this case only affects the following instructions using circular addressing mode:
ld.w, ld.d, ld.da.
Note: In the current TriCore1 CPU implementation, load accesses are initiated
from the DEC pipeline stage whilst store accesses are initiated from the
following EXE pipeline stage. To avoid memory port contention problems
when a load follows a store instruction, the CPU contains a single store
buffer. In the case where a store instruction (in EXE) is immediately
followed by a load instruction (in DEC), the store is directed to the CPU
store buffer and the load operation overtakes the store. The store is then
committed to memory from the store buffer on the next store instruction or
non-memory access cycle. The store buffer is only used for store
accesses to ‘local’ memories - LDRAM or DCache. Store instructions to
bus-based memories are always executed immediately (in-order). A store
buffer conflict is detected when a load instruction is encountered which
targets an address for which at least part of the requested data is currently
held in the CPU store buffer. In this store buffer conflict scenario, the load
instruction is cancelled, the store committed to memory from the store
TC1767, EES-AD, ES-AD, AD 14/73 Rel. 1.4, 11.12.2009