Errata Sheet - Infineon
Errata Sheet - Infineon
Errata Sheet - Infineon
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MultiCAN_AI.H006<br />
Time stamp influenced by<br />
resynchronization<br />
<strong>Errata</strong> <strong>Sheet</strong><br />
History List / Change Summary<br />
Table 6 Application Hints (cont’d)<br />
Hint Short Description Cha<br />
nge<br />
MultiCAN_TC.H002 Double Synchronization of receive input 64<br />
MultiCAN_TC.H003 Message may be discarded before<br />
transmission in STT mode<br />
MultiCAN_TC.H004 Double remote request 65<br />
OCDS_TC.H001<br />
OCDS_TC.H002<br />
OCDS_TC.H003<br />
OCDS_TC.H004<br />
PCP_TC.H004<br />
IOADDR may increment after aborted<br />
IO_READ_BLOCK<br />
Setting IOSR.CRSYNC during Application<br />
Reset<br />
Application Reset during host<br />
communication<br />
Device Identification by Application<br />
Software<br />
Invalid parity error generated by FPI write<br />
to PRAM<br />
PCP_TC.H005 Unexpected parity errors when address 0<br />
of CMEM is faulty<br />
PCP_TC.H006<br />
PCP_TC.H007<br />
BCOPY address alignment error may<br />
affect next channel FPI operation<br />
Do not use priority 0 to post interrupt to<br />
CPU<br />
PORTS_TC.H004 Using LVDS Ports in CMOS Mode 69<br />
PORTS_TC.H005<br />
Pad Input Registers do not capture<br />
Boundary-Scan data when BSD-mode<br />
signal is set to high<br />
PWR_TC.H005 Current Peak on V DDP during Power-up 70<br />
SSC_AI.H001<br />
Transmit Buffer Update in Slave Mode<br />
after Transmission<br />
Pa<br />
ge<br />
63<br />
64<br />
65<br />
66<br />
66<br />
67<br />
68<br />
68<br />
68<br />
69<br />
69<br />
70<br />
TC1767, EES-AD, ES-AD, AD 8/73 Rel. 1.4, 11.12.2009
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