Errata Sheet - Infineon

Errata Sheet
Functional Deviations
OCDS_AI.002 JTAG Instruction must be 8 bit long
The JTAG TAP controller implemented in all Infineon devices strictly adheres to
the standard IEEE 1149-1-2001. One side effect of this standard requires
special awareness, as it can cause severe errors.
Upon entry to the Capture-IR state the internal shift register is preloaded with
a constant, namely 01 H .
In the Shift-IR state the bits from the host are prepended, i.e. for each incoming
bit the old LSB is dropped, the remaining 7 bits are shifted right one bit position
and the incoming bit becomes the new MSB.
Upon entry to the Update-IR state the content of the internal shift register is
copied into the INSTRUCTION register unconditionally.
If the final state of the shift register happens to be a valid, but unintended
instruction, the device may enter a state very detrimental to the application. An
extreme example is the INTEST instruction, which turns off all outputs of the
device and is activated by instruction 01 H , i.e. if no bit at all is shifted in by the
host!
Recommendations
• Always shift in at least as many bits as the INSTRUCTION register holds.
This means 8 bit for Infineon devices.
• Check the bits returned via TDO: Must be 01 H followed by any data shifted
in excluding the last eight bits. This allows to “check the pipe” by shifting in
more than the required 8 bits.
• Use the protection offered by IOPATH: Keeping IOPATH different from 00 B
whenever possible will block all Boundary Scan functions.
• Do not use the DAP telegrams jtag_setIR and jtag_swapIR with n less than
eight.
• Use the CRC protected DAP interface if the application environment may
cause transmission errors on the JTAG signals.
TC1767, EES-AD, ES-AD, AD 40/73 Rel. 1.4, 11.12.2009