Errata Sheet - Infineon
Errata Sheet - Infineon
Errata Sheet - Infineon
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<strong>Errata</strong> <strong>Sheet</strong><br />
Functional Deviations<br />
(80000000 H to DFFFFFFF H ) will be halted until control of the DMA-LMB-Master<br />
is regained.<br />
In the case of a lock-up DMA-LMB-Master Read access, the next LMB access<br />
and associated response will have the following effect:<br />
• ERROR Response: The DMA-LMB-Master will treat this error response as<br />
its own. It will clear the lock-up state and return an error to the DMA access<br />
requester. Normal operation will then continue. Halted DMA access<br />
requests will resume. There is no corruption of the data flow.<br />
• NSC (No Special Condition) Acknowledge: The DMA-LMB-Master will treat<br />
this response as its own and again clear the lock-up state. The correct<br />
response to an unrecognised slave is an ERROR. Therefore the DMA-LMB-<br />
Master has signalled an invalid response back to the DMA access requester<br />
resulting in a corruption of the data flow.<br />
• RETRY Response: The DMA-LMB-Master will treat the retry response as its<br />
own and again clear the lock-up state. The access will be repeated to the<br />
same reserved address location again resulting in a lock-up condition. The<br />
sequence is broken by the first ERROR response or NSC acknowledge.<br />
The effect of a DMA-LMB-Master Write accesses to an unrecognised slave is<br />
the same as above with one exception:<br />
• If the next access is a Read access from the EBU-LMB-Slave then the DMA-<br />
LMB-Master will clear the lock-up state and respond as above. The EBU<br />
read completes but the data read by the Originator (e.g. TriCore) will be the<br />
write data of the DMA-LMB-Master Write access.<br />
The following should be noted:<br />
• At all times the DMA-FPI-Master and DMA-FPI-Slave remain accessible.<br />
• If the LMB-DMA-Master is in the lock-up state then accesses can still be<br />
made to the LMB bus by all other LMB-Masters (e.g. LFI-LMB-Master).<br />
Hint<br />
Do not perform a DMA channel, MLI, Cerberus or DMA-FPI-Slave access to a<br />
reserved address: all areas specified as reserved in the Memory Map Chapter,<br />
LMB Address Map Table must not be accessed by the DMA (ME, MLI,<br />
Cerberus).<br />
TC1767, EES-AD, ES-AD, AD 28/73 Rel. 1.4, 11.12.2009
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