Errata Sheet - Infineon

Errata Sheet
Functional Deviations
Workaround
None.
PCP_TC.027 Longer delay when clearing R7.IEN before atomic PRAM instructions
User Manual states that, when clearing R7.IEN, a delay of one instruction
before the mask becomes effective is needed. However, two instructions (for
example, two NOPs) are required between the clearing instruction and an
atomic PRAM instruction (MSET.PI/MCLR.PI/XCH.PI).
PCP_TC.032 Incorrect PCP behaviour following FPI timeouts (as a slave)
When PRAM is being accessed from the FPI bus and an FPI time-out occurs
then this can lead to corruption or loss of the current and subsequent FPI
accesses. In general an FPI time-out during an access to the PCP is unlikely
since FPI time-out is usually programmed for a large number of FPI clock cycles
and the only time that the FPI access cannot be immediately responded to by
the PCP is during the execution of atomic PRAM instructions. FPI accesses are
locked out for the entire duration of any sequence of back to back atomic PRAM
instructions. The combination of a low FPI time-out setting and long sequences
of atomic PRAM instructions could therefore result in FPI time-out.
Workaround
Keep the FPI time-out setting as high as possible and do not include long
sequences of back to back atomic PRAM instructions. If N is the highest amount
of back to back atomic PRAM instructions in any PCP channel program, FPI
time-out should at least be 10 times N.
PCP_TC.034 Usage of R7 requires delays between operations
If the following instruction sequence is used:
writing to R7
TC1767, EES-AD, ES-AD, AD 48/73 Rel. 1.4, 11.12.2009