Errata Sheet - Infineon
Errata Sheet - Infineon
Errata Sheet - Infineon
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Table 4 Functional Deviations (cont’d)<br />
Functional Short Description<br />
Deviation<br />
CPU_TC.107<br />
CPU_TC.108<br />
CPU_TC.109<br />
CPU_TC.110<br />
<strong>Errata</strong> <strong>Sheet</strong><br />
History List / Change Summary<br />
SYSCON.FCDSF may not be set after FCD<br />
Trap<br />
Incorrect Data Size for Circular<br />
Addressing mode instructions with wraparound<br />
Circular Addressing Load can overtake<br />
conflicting Store in Store Buffer<br />
Register Banks may be out of sync after<br />
FCU Trap<br />
CPU_TC.111 Imprecise Return Address for FCU Trap 21<br />
CPU_TC.113<br />
CPU_TC.114<br />
CPU_TC.115<br />
DMA_TC.013<br />
DMI_TC.014<br />
DMI_TC.015<br />
DMI_TC.016<br />
DMI_TC.017<br />
Interrupt may be taken during Trap entry<br />
sequence<br />
CAE Trap may be generated by UPDFL<br />
instruction<br />
Interrupt may be taken on exit from Halt<br />
mode with Interrupts disabled<br />
DMA-LMB-Master Access to Reserved<br />
Address Location<br />
Problems with Parity Handling in TriCore<br />
Data Memories<br />
LDRAM Access Limitations for 2KByte<br />
Data Cache Configurations<br />
CPU Deadlock possible when Cacheable<br />
access encounters Flash Double-Bit Error<br />
DMI line buffer is not invalidated by a write<br />
to OVC_OCON.DCINVAL if cache off.<br />
Cha<br />
nge<br />
Upd<br />
ate<br />
Upd<br />
ate<br />
FADC_TC.005 Equidistant multiple channel-timers 34<br />
FIRM_TC.010 Data Flash Erase Suspend Function New 35<br />
FLASH_TC.027 Flash erase time out of specification 37<br />
FLASH_TC.035 Flash programing time out of specification 38<br />
TC1767, EES-AD, ES-AD, AD 4/73 Rel. 1.4, 11.12.2009<br />
Pa<br />
ge<br />
12<br />
12<br />
16<br />
19<br />
21<br />
25<br />
26<br />
27<br />
29<br />
29<br />
30<br />
32
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