Errata Sheet - Infineon

Workaround
Errata Sheet
Functional Deviations
As described previously, this problem should not be encountered during normal
operation and will only be triggered in the case of a double-bit error being
detected in an access to the on-chip Flash.
However, in order to remove the possibility of encountering this issue, all load
accesses to cacheable addresses within the on-chip Flash should be made
using natural alignment - word transfers should be word aligned, double-word
transfers double-word aligned.
It is also possible to check for the occurrence of this problem by having some
other master, such as the PCP, periodically poll the LBCU LEATT register to
check for the occurrence of LMB error conditions, specifically if one is detected
during a BTR2 read transfer from the DMI, as reported by LEATT.OPC and
LEATT.TAG.
DMI_TC.017 DMI line buffer is not invalidated by a write to
OVC_OCON.DCINVAL if cache off.
A problem exists whereby the DMI line buffer is not invalidated by a write to
OVC_OCON.DCINVAL when operating with the D-cache turned off. This
means that the user cannot rely on a write to OVC_OCON.DCINVAL to make
sure that any stale data in the DMI line buffer is invalidated. This can be a
problem for users who want to use the OVC_OCON.DCINVAL bit to ensure
coherency between the DMI and background memory.
It should be noted that this problem is not encountered when the D-cache is
turned on. When the D-cache is turned on, writing a one to
OVC_OCON.DCINVAL will correctly invalidate all clean cache entries and
invalidate the DMI line buffer. The problem only concerns systems with no
cache or systems where the cache is turned off.
Detailed description
D-Cache turned on:
When D-cache is turned on, the DMI line buffer is only used as a performance
enhancement mechanism with no logical existence to the user. It is therefore
not operating as a micro-cache and the current issue does not apply. When the
TC1767, EES-AD, ES-AD, AD 32/73 Rel. 1.4, 11.12.2009