Errata Sheet - Infineon

Errata Sheet
Functional Deviations
cases detailed above which may lead to incorrect behaviour, one NOP
instruction should be inserted prior to the load or store instruction using circular
addressing mode.
...
LDA a8, 0xD000000E ; Address of un-aligned load
LDA a12, 0xD0000820 ; Circular Buffer Base
LDA a13, 0x00180014 ; Circular Buffer Limit and Index
...
ld.w d6, [a8] ; Un-aligned load, split 16+16
add d4, d3, d2 ; Optional IP instruction
nop
; Bug workaround
st.d [a12/a13+c], d0/d1 ; Circular Buffer wrap, 32+32
...
CPU_TC.109 Circular Addressing Load can overtake conflicting Store in
Store Buffer
In a specific set of circumstances, a load instruction using circular addressing
mode may overtake a conflicting store held in the TriCore1 CPU store buffer.
The problem occurs in the following situation:
• The CPU store buffer contains a byte store instruction, st.b, targeting the
base address + 0x1 of a circular buffer.
• A word load instruction, ld.w, is executed using circular addressing mode,
targetting the same circular buffer as the buffered byte store.
• This word load is only half-word aligned and encounters the circular buffer
wrap-around condition such that the second, wrapped, access of the load
instruction to the bottom of the circular buffer targets the same address as
the byte store held in the store buffer.
Additionally, one of the following further conditions must also be present for the
problem to occur:
• The circular buffer base address for the word load is double-word but not
quad-word (128-bit) aligned - i.e. the base address has bits (3:0) = 0x8 with
the conflicting byte store having address bits (3:0) = 0x9, OR,
• The circular buffer base address for the word load is quad-word (128-bit)
aligned and the circular buffer size is an odd number of words - i.e. the base
TC1767, EES-AD, ES-AD, AD 16/73 Rel. 1.4, 11.12.2009