Mathcad - ee217projtodonew2.mcd

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maximum. So why does A 1 increase intially for small devices and decrease for large devices? For small devices the device is operating well below the maximum frequency, f T , for the device. In this region capacitive effects are less significant and resistive effects are more significant. Here A 1 is approximately gm/(1+g m *r e0 /N). As the device size gets larger the effective degeneration is reduced, which increases the linear gain, A 1 . However for large devices, the base emitter capacitance increases to the point, approaching f T , where the capacitive effects become significant, the effective device f T is reduced with increasing device size, and we see losses in the high frequency gain. The resistive and capacitive effects tend to cancel at some point, and which gain only varies slowly as a function of device size. Now we must answer the more important question: Why does A 3 decrease for large devices? If we look carefully at the equations for the intercept point, we notice A 3 is a strong function of A 1 3. If this is true A 3 will have a similar shape to A 1 , except exaggerated more. This is exactly what we see if we plot A 1 and A 3 independently as a function of frequency. 0.05 0.04 Linear and Third-Order Terms 0.03 0.02 0.01 0 0 20 40 60 80 100 Device Size Linear Term Third Order Term Fig. 33: A1 and A3 vs. Device Size Overall LNA Figure of Merit The input referred minimum detectable signal with an amplifier is defined below for a signal of a given bandwidth and noise figure. The noise figure is given in dB and MDS in dBm. MDS( BW, NF) k. T. BW 3 NF The spurious free dynamic range, DR f , is defined as the ratio between vmax and vmin, where vmax the input signal where the IM 3 just breaks the noise floor defined by vmin. IP 3 is specified in dBm, G in dB, and MDS in dBm. DR f IP 3 , G, MDS 2 . 3 IP 3 G MDS The dynamic range is defined similarly with the 1dB compression point defined as vmax. DR P 1dB , G, MDS P 1dB G MDS
Optimizing Area and Current I C 0.006 Unitless Guesses at optimal bias current and device size N 50 NF N, I C NF min N, I . C A, s Given I C > 0 Bias Current Constraint N> 0 Device Size Constraints G avail N, I . C A, s G goaldB IP 3 N, I . C A, Z nopt N, I . C A, s , f, ∆f IP 3goaldBm 46.572 P Minimize NF, N, I C P = 7.277 . 10 3 N opt P 1 N opt 46.572 I Copt > Available Power Gain Constraint > Intercept Point Constraints = Optimal Device Size P . 2 A I Copt = 7.277 mA Optimal Bias Current Size NF min N opt , I Copt , s = 0.84 dB Optimal Minimum Noise Figure , , , s , f, ∆f = 10 dBm Optimal Intercept Point IP 3 N opt , I Copt Z nopt N opt I Copt Z S N opt , I Copt , s = 62.211 5.063i ohm Optimal Source Impedance Z L N opt , I Copt , s = 110.436 61.585i ohm Optimal Load Impedance G avail N opt , I Copt , s = 13.5 dB Optimal Gain Package (Bonding Wire/ Bonding Pad) Deimbedding The actual impedance matching network is outside of the chip, but calculations for the desired source and load impedances were calculated for the device inside the chip. These internal source and load impedances must be transformed into the source and load impedances seen by the matching networks. To find these conversion equations we first write the equation for impedance seen by the device, Z S , given an impedance seen by the outside of the chip, Z Schip . Then we use this equation to solve for Z Schip in terms of Z S . Source Impedance Bonding Pad/Wire Deimbedding Z Schip L bond C pad Z S AMP Fig. 34: Circuit Used to Solve for Source Impedance Bonding Deimbedding
Page 1 and 2: 'HVLJQDQG$QDO\VLVRID *+]/RZ1RLVH$PS
Page 3 and 4: Introduction Low noise amplifiers a
Page 5 and 6: ∆f: The frequency spacing of the
Page 7 and 8: Architecture Selection Amplifier Ev
Page 9 and 10: Common Base Amplifier To find the d
Page 11 and 12: KCL N, I C , s, Z S , Z L 1 1 1 Z S
Page 13 and 14: 100 10 1 0.1 0.01 0.01 0.1 1 10 100
Page 15 and 16: Ballast Resistor Sizing The term ba
Page 17 and 18: 2000 Ballast Resistor (ohms) 1500 1
Page 19 and 20: Z popt SZ , 0 ∆ S . 11 , S 22 , S
Page 21 and 22: Solve r . b i . bn Z . e β β . V
Page 23 and 24: Noise Correlation Except in special
Page 25 and 26: n is the noise resistance represent
Page 27 and 28: Optimal Source Impedance to Trade-O
Page 29 and 30: Gain Analysis Z2Γ( Z) Z Z G T Γ G
Page 31: A 3 N, I C , Z S , s 1 , s 2 , s 3
Page 35 and 36: Impedance Matching High-pass impeda
Page 37 and 38: Low Frequency Stabilization It is d
Page 39 and 40: To insure stability over the spectr
Page 41: It is possible to use on-chip induc
Page 49: ... . 1 s 1 s 2 s . 3 C je N, I . C

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