Controller - Institute of Transportation Engineers

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RTS - Request to Send R/W - <strong>Controller</strong> Unit Read/Write Control Line RxD - Received Data SCI - Serial Communications Interface SDLC - Synchronous Data Link Control S - Logic State s - second Second Sourced - Produced by more than one manufacturer SRAM - Static Random Access Memory Device SW - Switch TB - Terminal Block TOD - Time Of Day Clock Triac - Silicon-Controlled Rectifier which controls power bilaterally in an AC switching circuit TTL - Transistor-Transistor Logic Thumb Screw - (TSD ) A retractable screw fastener with projecting Device stainless steel screw, spring and natural aluminum knob finish. (TSD No.2 shall be flat black.) TxD - Transmitted Data u - Micro TSD No.1 - 8-32 SOUTHCO #47-62-301-20 or equal. TSD No.2 - 8-32 SOUTHCO #47-62-301-60 or equal. TSD No.3 - M3 SOUTHCO #47-82-101-10 or equal. UL - Underwriter's Laboratories, Inc. VAC - Voltage Alternating Current (root mean square) Standard for the ATC – Type 2070 March 29, 2001 110
VDC - Voltage Direct Current VME - Versa Module Eurocard, VMEbus Standard IEEE P1014/D1.2 x - Number Value XX - Manufacturer's Option WDT - Watchdog Timer: A monitoring circuit, external to the device watched, which senses an Output Line from the device and reacts Standard for the ATC – Type 2070 March 29, 2001 111
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A Recommended Standard of the Joint
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Table of Contents 1 FOREWORD.......
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4.4.3 CPU Active Indicator.........
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2 INTRODUCTION 2.1 Overview The Adv
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Type 2070 Controller Unit - Type 20
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3.1.5.3 Cold Rolled Steel Sheet, Ro
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The potentiometer power rating shal
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3.2.13 Wiring, Cabling, and Harness
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Insulation Resistance: 5,000 megohm
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The equipment shall be engineered f
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3.5.1.5 Each PCB connector edge sha
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All circuits, unless otherwise note
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3.7.5.2 The quality control procedu
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The EIA-485 Line Drivers/Receivers
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The 2070-1B CPU shall not draw more
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4.2.4 Transition Board A TRANSITION
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timer34 = access to MC68360's inter
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An Async-Communications Serial Devi
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Note: The inhibit DCD selection has
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4.2.7.2.9.2 Setting Hardware Clock
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4.2.7.4.3 The Error Handler error r
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4.2.7.6.6 OS-9 compliant header fil
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4.3.5.4 One KHz Reference A synchro
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Input scanning shall begin at I0 (b
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Generate the CRC value Generate the
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SCC Transmit Error Count Transmit E
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e - r - S - A one-byte leading edge
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(Type Number = 182) 1 0 1 1 0 1 1 0
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MC Timestamp NMSB x x x x x x x x B
Page 59 and 60: '0' - immediately upon command rece
Page 61 and 62: The timeout value shall be in the r
Page 63 and 64: Each character shall be composed of
Page 65 and 66: 4.4.5.8 Cursor positioning shall be
Page 67 and 68: supply compartment from the back of
Page 69 and 70: Less than 0.2% rms, 1% peak to peak
Page 71 and 72: 4.7 Chapter Details TABLE OF CONTEN
Page 73 and 74: Standard for the ATC - Type 2070 Ma
Page 87 and 88: 2. Modulation: Phase coherent frequ
Page 89 and 90: external screws, except where calle
Page 91 and 92: 5.4.2.10 A 22-line minimum HAR 2 Ha
Page 93 and 94: Type 2070N - NEMA Module, Back Cove
Page 105 and 106: 6 GLOSSARY 6.1.1 Terms and Abbrevia
Page 107 and 108: EEPROM - Electrically Erasable, Pro
Page 109: NETA - National Electrical Testing
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Controller - Institute of Transportation Engineers

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