Controller - Institute of Transportation Engineers

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Case Output Data Bit Output Control Bit Function A 0 0 Output in the OFF state B 1 1 Output is a square wave, synchronized to the LINESYNC signal. When LINESYNC is ON (1), the output is OFF, and when LINESYNC is OFF (0), the output is ON. C 0 1 Output is a square wave, synchronized to the LINESYNC signal. When LINESYNC is ON (1), the output is ON, and when LINESYNC is OFF (0), the output is OFF D 1 0 Output is in the ON state. 4.3.8.4.1 In Case A above, the corresponding output shall be turned OFF if previously ON and if previously OFF remain OFF until otherwise configured. For half-cycle switching (cases B and C), all outputs to be changed shall be changed within 50 µs after the corresponding LINESYNC transition and shall remain in the same state during the entire half cycle. In Case D above, the corresponding output shall be turned ON if previously OFF and if previously ON remain ON until otherwise configured. All outputs shall not change state unless configured to do so. 4.3.8.5 Interrupts All interrupts shall be capable of asynchronous operation with respect to all processing and all other interrupts. MILLISECOND Interrupt shall be activated by the 1 KHz reference once per ms. An MC timestamp rollover flag set by MC rollover shall be cleared only on command. LINESYNC Interrupt - This interrupt shall be generated by both the 0-1 and 1-0 transitions of the LINESYNC signal. The LINESYNC interrupt shall monitor the MC interrupt and set the MC error flag if there has not been an interrupt from the 1 KHz source for 0.5 seconds ( ≥ 60 consecutive LINESYNC interrupts). The LINESYNC interrupt shall synchronize the 1 KHz time reference with the 0-1 transition of the LINESYNC signal once a second. A LINESYNC error flag shall be set if the LINESYNC interrupt has not successfully executed for 0.5 seconds or longer ( ≥ 500 consecutive millisecond interrupts). 4.3.8.6 Communication Service Routine A low-level communication service routine shall be provided to handle reception, transmission, and EIA-485 communication faults. The communication server shall automatically: For Transmission: Generate the opening and closing flags Standard for the ATC – Type 2070 March 29, 2001 48
Generate the CRC value Generate the abort sequence (minimum of 8 consecutive '1' bits) when commanded by the FCU Provide zero bit insertion For Receiving: Detect the opening and closing flags Provide address comparison, generating an interrupt for messages addressed to the I/O Module, and ignoring messages not addressed to the I/O Module Strip out inserted zeros Calculate the CRC value, compare it to the received value, and generate an interrupt on an error Generate an interrupt if an abort sequence is received 4.3.8.7 Communication Processing The task shall be to process the command messages received from the CPU Module, prepare, and start response transmission. The response message transmission shall begin within 4 ms of the receipt of the received message. The time from the receipt of message to the completion of the commanded task shall not exceed 70ms. 4.3.8.8 Input Processing This task shall process the raw input data scanned in by the 1 ms interrupt routine, perform all filtering, and maintain the transition queue entries. 4.3.9 Data Communications Protocols Protocols - All communication with the CPU Module shall be SDLC-compatible command-response protocol, support 0 bit stuffing, and operate at a data rate of 614.4 Kbps. The CPU Module shall always initiate the communication and should the command frame be incomplete or in error, no FI/O response shall be transmitted. The amount of bytes of a command or response is dependent upon the I/O Module identification. 4.3.9.1.1 The frame type shall be determined by the value of the first byte of the message. The command frames type values 112-127 and associated response frame type values 240- 255 are allocated to the Contractor diagnostics. All other frame types not called out are reserved. The command-response Frame Type values and message times shall be as follows: Frame Types Standard for the ATC – Type 2070 March 29, 2001 49
Page 1 and 2: A Recommended Standard of the Joint
Page 3 and 4: Table of Contents 1 FOREWORD.......
Page 5 and 6: 4.4.3 CPU Active Indicator.........
Page 7 and 8: 2 INTRODUCTION 2.1 Overview The Adv
Page 9 and 10: Type 2070 Controller Unit - Type 20
Page 11 and 12: 3.1.5.3 Cold Rolled Steel Sheet, Ro
Page 13 and 14: The potentiometer power rating shal
Page 15 and 16: 3.2.13 Wiring, Cabling, and Harness
Page 17 and 18: Insulation Resistance: 5,000 megohm
Page 19 and 20: The equipment shall be engineered f
Page 21 and 22: 3.5.1.5 Each PCB connector edge sha
Page 23 and 24: All circuits, unless otherwise note
Page 25 and 26: 3.7.5.2 The quality control procedu
Page 27 and 28: The EIA-485 Line Drivers/Receivers
Page 29 and 30: The 2070-1B CPU shall not draw more
Page 31 and 32: 4.2.4 Transition Board A TRANSITION
Page 33 and 34: timer34 = access to MC68360's inter
Page 35 and 36: An Async-Communications Serial Devi
Page 37 and 38: Note: The inhibit DCD selection has
Page 39 and 40: 4.2.7.2.9.2 Setting Hardware Clock
Page 41 and 42: 4.2.7.4.3 The Error Handler error r
Page 43 and 44: 4.2.7.6.6 OS-9 compliant header fil
Page 45 and 46: 4.3.5.4 One KHz Reference A synchro
Page 47: Input scanning shall begin at I0 (b
Page 51 and 52: SCC Transmit Error Count Transmit E
Page 53 and 54: e - r - S - A one-byte leading edge
Page 55 and 56: (Type Number = 182) 1 0 1 1 0 1 1 0
Page 57 and 58: MC Timestamp NMSB x x x x x x x x B
Page 59 and 60: '0' - immediately upon command rece
Page 61 and 62: The timeout value shall be in the r
Page 63 and 64: Each character shall be composed of
Page 65 and 66: 4.4.5.8 Cursor positioning shall be
Page 67 and 68: supply compartment from the back of
Page 69 and 70: Less than 0.2% rms, 1% peak to peak
Page 71 and 72: 4.7 Chapter Details TABLE OF CONTEN
Page 73 and 74: Standard for the ATC - Type 2070 Ma
Page 87 and 88: 2. Modulation: Phase coherent frequ
Page 89 and 90: external screws, except where calle
Page 91 and 92: 5.4.2.10 A 22-line minimum HAR 2 Ha
Page 93 and 94: Type 2070N - NEMA Module, Back Cove
Page 99 and 100:
Standard for the ATC - Type 2070 Ma
Page 101 and 102:
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Page 105 and 106:
6 GLOSSARY 6.1.1 Terms and Abbrevia
Page 107 and 108:
EEPROM - Electrically Erasable, Pro
Page 109 and 110:
NETA - National Electrical Testing
Page 111:
VDC - Voltage Direct Current VME -
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Controller - Institute of Transportation Engineers

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