Controller - Institute of Transportation Engineers

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Module I/0 Module Minimum Maximum Description Command Response Message Time Message Time 0-43 128-171 Reserved for NEMA TS-2 49 177 Request Module Status 250 µs 275 us 50 178 MILLISECOND CTR. Mgmt. 222.5 µs 237.5 us 51 179 Configure Inputs 344.5 µs 6.8750 ms 52 180 Poll Raw Input Data 317.5 µs 320 µs 53 181 Poll Filtered Input Data 317.5 µs 320 µs 54 182 Poll Input Transition Buffer 300 µs 10.25 ms 55 183 Command Outputs 405 µs 410 µs 56 184 Config. Input Tracking Functions 340 µs 10.25 ms 57 185 Config. Complex Output Functions 340 µs 6.875 ms 58 186 Configure Watchdog 222.5 µs 222.5 µs 59 187 Controller Identification 222.5 µs 222.5 µs 60 188 I/O Module Identification 222.5 µs 222.5 µs 61-62 189-190 Reserved (note below) 63 191 Poll variable length raw input 317.5 us 320 us 64 192 Variable length command outputs 405 us 410 us 4.3.9.1.2 Messages 61 / 189 and 62 / 190 are reserved for ITS Cabinet Frame Types. Message 63 / Message 191 shall be the same as Message 52 / 180 except Byte 2 of Message 180 response shall denote the following number of inputs bytes. Message 64 / 192 shall be the same as Message 55 / 183 except Byte 2 of the Message 55 Command shall denote the number of output data bytes along with the following output data. 4.3.9.2 Request Module Status The Command shall be used to request FI/O status information response. Command/response frames are as follows: Request Module Status Command Description msb lsb Byte Number (Type Number = 49) 0 0 1 1 0 0 0 1 Byte 1 Reset Status Bits P E K R T M L W Byte 2 Request Module Status Response Description msb lsb Byte Number (Type Number = 177) 1 0 1 1 0 0 0 1 Byte 1 System Status P E K R T M L W Byte 2 SCC Receive Error Count Receive Error Count Byte 3 Standard for the ATC – Type 2070 March 29, 2001 50
SCC Transmit Error Count Transmit Error Count Byte 4 MC Timestamp MSB MC Timestamp MSB Byte 5 MC Timestamp NMSB MC Timestamp NMSB Byte 6 MC Timestamp NLSB MC Timestamp NLSB Byte 7 MC Timestamp LSB MC Timestamp LSB Byte 8 4.3.9.2.1 The response status bits are defined as follows: 4.3.9.2.2 P - Indicates FI/O hardware reset E - Indicates a communications loss of greater than 2 seconds K - Indicates the Datakey has failed or is not present R - Indicates that the EIA-485 receive error count byte has rolled over T - Indicates that the EIA-485 transmit error count byte has rolled over M - Indicates an error with the MC interrupt L - Indicates an error in the LINESYNC W - Indicates that the FI/O has been reset by the Watchdog The FI/O status byte shall be updated (set to '1') to reflect the faults noted in clause 4.3.9.2.1. Each status bit shall only be reset (set to '0') when the corresponding bit of the Request Module Status Command is a '1'. The Request Module Status Response shall report the current status (subsequent to reset and sampling). 4.3.9.2.3 The FI/O shall count the number of errored frames the FI/O Communications Processor reports. Separate counts shall be maintained for transmit and received frames. When a individual count rolls over (255-0), the corresponding roll-over flag shall be set. 4.3.9.2.4 FI/O modules with Datakey: On NRESET transition to High or immediately prior to any interrogation of the Datakey, the FI/O shall test the presence of the Key. If absent, Status Bit “K” shall be set to '1' and no interrogation shall take place. If an error occurs during the interrogation, Status Bit “K” shall be set to '1'. FI/O modules without Datakey: Status Bit "K" shall always be set to '1' 4.3.9.2.5 The MC timestamp value shall be sampled just prior to the Request Module Status Response. Standard for the ATC – Type 2070 March 29, 2001 51
Page 1 and 2: A Recommended Standard of the Joint
Page 3 and 4: Table of Contents 1 FOREWORD.......
Page 5 and 6: 4.4.3 CPU Active Indicator.........
Page 7 and 8: 2 INTRODUCTION 2.1 Overview The Adv
Page 9 and 10: Type 2070 Controller Unit - Type 20
Page 11 and 12: 3.1.5.3 Cold Rolled Steel Sheet, Ro
Page 13 and 14: The potentiometer power rating shal
Page 15 and 16: 3.2.13 Wiring, Cabling, and Harness
Page 17 and 18: Insulation Resistance: 5,000 megohm
Page 19 and 20: The equipment shall be engineered f
Page 21 and 22: 3.5.1.5 Each PCB connector edge sha
Page 23 and 24: All circuits, unless otherwise note
Page 25 and 26: 3.7.5.2 The quality control procedu
Page 27 and 28: The EIA-485 Line Drivers/Receivers
Page 29 and 30: The 2070-1B CPU shall not draw more
Page 31 and 32: 4.2.4 Transition Board A TRANSITION
Page 33 and 34: timer34 = access to MC68360's inter
Page 35 and 36: An Async-Communications Serial Devi
Page 37 and 38: Note: The inhibit DCD selection has
Page 39 and 40: 4.2.7.2.9.2 Setting Hardware Clock
Page 41 and 42: 4.2.7.4.3 The Error Handler error r
Page 43 and 44: 4.2.7.6.6 OS-9 compliant header fil
Page 45 and 46: 4.3.5.4 One KHz Reference A synchro
Page 47 and 48: Input scanning shall begin at I0 (b
Page 49: Generate the CRC value Generate the
Page 53 and 54: e - r - S - A one-byte leading edge
Page 55 and 56: (Type Number = 182) 1 0 1 1 0 1 1 0
Page 57 and 58: MC Timestamp NMSB x x x x x x x x B
Page 59 and 60: '0' - immediately upon command rece
Page 61 and 62: The timeout value shall be in the r
Page 63 and 64: Each character shall be composed of
Page 65 and 66: 4.4.5.8 Cursor positioning shall be
Page 67 and 68: supply compartment from the back of
Page 69 and 70: Less than 0.2% rms, 1% peak to peak
Page 71 and 72: 4.7 Chapter Details TABLE OF CONTEN
Page 73 and 74: Standard for the ATC - Type 2070 Ma
Page 87 and 88: 2. Modulation: Phase coherent frequ
Page 89 and 90: external screws, except where calle
Page 91 and 92: 5.4.2.10 A 22-line minimum HAR 2 Ha
Page 93 and 94: Type 2070N - NEMA Module, Back Cove
Page 101 and 102:
Standard for the ATC - Type 2070 Ma
Page 103 and 104:
Standard for the ATC - Type 2070 Ma
Page 105 and 106:
6 GLOSSARY 6.1.1 Terms and Abbrevia
Page 107 and 108:
EEPROM - Electrically Erasable, Pro
Page 109 and 110:
NETA - National Electrical Testing
Page 111:
VDC - Voltage Direct Current VME -
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Controller - Institute of Transportation Engineers

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