Controller - Institute of Transportation Engineers
Controller - Institute of Transportation Engineers
Controller - Institute of Transportation Engineers
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level, the appropriate MCB Circuitry shall shift from standby power to incoming +5<br />
VDC.<br />
4.2.3.4 RAM Memory<br />
A minimum <strong>of</strong> 4 MB <strong>of</strong> DRAM, organized in 32-bit words, shall be provided. A<br />
minimum <strong>of</strong> 512 KB <strong>of</strong> SRAM, organized in 16- or 32-bit words, shall be provided. The<br />
SRAM shall draw no more than 50 µA at +5 VDC in Standby Mode. The time from the<br />
presentation <strong>of</strong> valid RAM address, select lines, and data lines to the RAM device to the<br />
acceptance <strong>of</strong> data by the RAM device shall not exceed 80 ns and shall be less as required<br />
to fulfill zero wait state RAM device write access under all operational conditions.<br />
4.2.3.5 FLASH Memory<br />
A minimum <strong>of</strong> 4 MB <strong>of</strong> FLASH Memory, organized in 16- or 32-bit words, shall be<br />
provided. The MCB shall be equipped with all necessary circuitry for writing to the<br />
FLASH Memory under program control. No more than 1 MB <strong>of</strong> FLASH Memory shall<br />
be used for Boot Image (List) and a minimum <strong>of</strong> 3 MB shall be available for AGENCY<br />
use.<br />
4.2.3.6 Time-<strong>of</strong>-Day Clock<br />
A s<strong>of</strong>tware settable hardware Time-<strong>of</strong>-Day (TOD) clock shall be provided. The Time-<strong>of</strong>-<br />
Day Clock shall be maintained to within + 0.005% at 20 o C (68 o F) and to within + 0.02%<br />
over the specified operating temperature range as compared to Coordinated Universal<br />
Time (WWV) standard for a period <strong>of</strong> thirty days during periods when AC power is not<br />
applied. The clock shall be aligned to a minimum fractional second resolution <strong>of</strong> 10 ms<br />
and shall track seconds, minutes, hours, day <strong>of</strong> month, month, and year.<br />
4.2.3.7 CPU Reset<br />
A s<strong>of</strong>tware-driven CPU RESET signal (Active LOW) shall be provided to reset other<br />
controller systems. The signal output shall be driver capable <strong>of</strong> sinking 30 mA at 30<br />
VDC. Execution <strong>of</strong> the program module “CPURESET” in the boot image shall assert the<br />
CPU RESET signal once.<br />
4.2.3.8 CPU Activity Indicator<br />
An open-collector output, capable <strong>of</strong> sinking 30 mA at 30 VDC, shall be provided to<br />
drive the Front Panel Assembly CPU Activity LED INDICATOR.<br />
4.2.3.9 Tick Timer<br />
The OS-9 Operating System TICK Timer shall be derived from each transition <strong>of</strong><br />
LINESYNC with a tick rate <strong>of</strong> 120 ticks per second.<br />
Standard for the ATC – Type 2070 March 29, 2001<br />
30
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