S845WD1-E Server Board - Viglen Download

Functional Architecture
S845WD1-E Server Board TPS
3.7 Clock Generation and Distribution
All buses on the S845WD1-E baseboard operate using synchronous clocks. Clock
synthesizer/driver circuitry on the baseboard generates clock frequencies and voltage levels as
required, including the following:
• 100/133-MHz at 2.5 V & 3.3 V logic levels: For the mPGA478 socket, the MCH, and the
ITP port.
• 66 MHz at 3.3 V logic levels: For the MCH, RAID controller and the AGP clocks.
• 33.3 MHz at 3.3 V logic levels: For the PCI slots and devices.
• 14.318 MHz at 3.3V logic levels: ICH2 and Super I/O clocks.
The synchronous clock sources on the S845WD1-E baseboard are:
• 100/133-MHz host clock generator for processor, MCH, Memory DIMMs, and the ITP.
• 66-MHz clock for MCH, RAID controller and the AGP clocks.
• 48-MHz clock for USB.
• 33.3-MHz PCI reference clock.
• 14.318 MHz ICH2 and Super I/O clocks.
The S845WD1-E baseboard also provides asynchronous clock generators:
• 25-MHz clocks for the embedded network interface controllers.
• 29.4989-MHz clock for the embedded video controller.
• 32-KHz clock for the RTC.
3.8 PCI I/O Subsystem
The primary I/O bus for the S845WD1-E server board is PCI, with one independent PCI bus. The
PCI bus complies with the PCI Local Bus Specification, Rev 2.2. The PCI bus is directed
through the Intel 82801BA I/O Controller Hub (ICH2). The table below lists the characteristics of
the PCI bus.
Table 8. PCI Bus Characteristics
Voltage Width Speed Type Comments
5 V 32-bits 33 MHz
Independent
Bus
Supports full-length cards
22
Intel order number A93850-002
Revision 2.0