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S845WD1-E Server Board - Viglen Download

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Maps and Interrupts<br />

<strong>S845WD1</strong>-E <strong>Server</strong> <strong>Board</strong> TPS<br />

4.6 PCI Interrupt Routing Map<br />

The PCI specification specifies how interrupts can be shared between devices attached to the<br />

PCI bus. In most cases, the small amount of latency added by interrupt sharing does not affect<br />

the operation or throughput of the devices. In special cases where maximum performance is<br />

needed from a device, a PCI device should not share an interrupt with other PCI devices. Use<br />

the following information to avoid sharing an interrupt with a PCI add-in card.<br />

PCI devices are categorized as follows to specify their interrupt grouping:<br />

• INTA: By default, all add-in cards that require only one interrupt are in this category. For<br />

almost all cards that require more than one interrupt, the first interrupt on the card is also<br />

classified as INTA.<br />

• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts<br />

is classified as INTB. (This is not an absolute requirement.)<br />

• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a<br />

fourth interrupt is classified as INTD.<br />

The ICH2 has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt<br />

sources either on-board or from a PCI add-in card connect to one of these PIRQ signals. Some<br />

PCI interrupt sources are electrically tied together on the <strong>S845WD1</strong>-E server board and<br />

therefore share the same interrupt. Table 16 shows an example of how the PIRQ signals are<br />

routed on the <strong>S845WD1</strong>-E server board.<br />

Using Table 16 as a reference, assume an add-in card using INTB is plugged into PCI bus<br />

connector 3. In PCI bus connector 3, INTB is connected to PIRQB, which is already connected<br />

to the SMBus. The add-in card in PCI bus connector 3 now shares interrupts with these onboard<br />

interrupt sources.<br />

Table 16. PCI Interrupt Routing Map<br />

PCI Interrupt Source<br />

PIRQ Assignment for Woodruff<br />

A B C D E F G H IDSEL Req/Gnt<br />

AGP connector A B<br />

ICH2 USB controller 1<br />

A<br />

SMBus controller A<br />

ICH2 USB controller 2<br />

A<br />

ICH2 Audio/Modem<br />

82550 LAN#1 A 28 1<br />

82550 LAN#2 A 29 2<br />

ATA RAID A 30 3<br />

ATI Rage A 31 4<br />

PCI bus connector 1 D A B C 25 0<br />

PCI bus connector 2 C D A B 26 5<br />

PCI bus connector 3 B C D A 27 5<br />

32<br />

Intel order number A93850-002<br />

Revision 2.0

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