P89V51RB2/RC2/RD2 8-bit 80C51 5 V low power 16/32 ... - NetMedia

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NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core Table 64. External clock drive Symbol Parameter Oscillator Unit 40 MHz Variable Min Max Min Max f osc oscillator frequency - - 0 40 MHz T cy(clk) clock cycle time 25 - - - ns t CHCX clock HIGH time 8.75 - 0.35T cy(clk) 0.65T cy(clk) ns t CLCX clock LOW time 8.75 - 0.35T cy(clk) 0.65T cy(clk) ns t CLCH clock rise time - 10 - - ns t CHCL clock fall time - 10 - - ns V DD − 0.5 V 0.45 V 0.2V DD + 0.9 V 0.2V DD − 0.1 V t CHCL t CLCX t CLCH T cy(clk) t CHCX 002aaa907 Fig 34. External clock drive waveform Table 65. Serial port timing Symbol Parameter Oscillator Unit 40 MHz Variable Min Max Min Max T XLXL serial port clock cycle time 0.3 - 12T cy(clk) - µs t QVXH output data set-up to clock rising 117 - 10T cy(clk) − 133 - ns edge time t XHQX output data hold after clock rising 0 - 2T cy(clk) − 50 - ns edge time t XHDX input data hold after clock rising edge 0 - 0 - ns time t XHDV input data valid to clock rising edge time - 117 - 10T cy(clk) − 133 ns P89V51RB2_RC2_RD2_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 1 May 2007 68 of 80
NXP Semiconductors P89V51RB2/RC2/RD2 8-bit microcontrollers with 80C51 core instruction 1 2 3 4 5 6 7 8 ALE 0 t XLXL clock output data write to SBUF input data clear RI t QVXH t XHDV t XHQX 0 1 2 3 4 5 6 7 t XHDX set TI valid valid valid valid valid valid valid valid set RI 002aaa552 Fig 35. Shift register mode timing waveforms Table 66. SPI interface timing Symbol Parameter Conditions Variable clock f osc =18MHz Unit Min Max Min Max f SPI SPI operating frequency 0 T cy(clk) / 4 0 10 MHz T SPICYC SPI cycle time see Figure 36, 37, 38, 39 4T cy(clk) - 222 - ns t SPILEAD SPI enable lead time see Figure 38, 39 250 - 250 - ns t SPILAG SPI enable lag time see Figure 38, 39 250 - 250 - ns t SPICLKH SPICLK HIGH time see Figure 36, 37, 38, 39 2T cy(clk) - 111 - ns t SPICLKL SPICLK LOW time see Figure 36, 37, 38, 39 2T cy(clk) - 111 - ns t SPIDSU SPI data set-up time master or slave; see 100 - 100 - ns Figure 36, 37, 38, 39 t SPIDH SPI data hold time master or slave; see 100 - 100 - ns Figure 36, 37, 38, 39 t SPIA SPI access time see Figure 38, 39 0 80 0 80 ns t SPIDIS SPI disable time see Figure 38, 39 0 160 - 160 ns t SPIDV SPI enable to output see Figure 36, 37, 38, 39 - 111 - 111 ns data valid time t SPIOH SPI output data hold see Figure 36, 37, 38, 39 0 - 0 - ns time t SPIR SPI rise time see Figure 36, 37, 38, 39 SPI outputs (SPICLK, - 100 - 100 ns MOSI, MISO) SPI inputs (SPICLK, - 2000 - 2000 ns MOSI, MISO, SS) t SPIF SPI fall time see Figure 36, 37, 38, 39 SPI outputs (SPICLK, - 100 - 100 ns MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) - 2000 - 2000 ns P89V51RB2_RC2_RD2_4 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 04 — 1 May 2007 69 of 80
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P89V51RB2/RC2/RD2 8-bit 80C51 5 V low power 16/32 ... - NetMedia

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