IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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Table 23. BAUD RATE AT 1.843 Mhz Desired Divisor Used Percent Error Baud to Generate Difference Between Rate 16x Clock Desired & Actual Decimal Hex 50 2304 '900' - 75 1536 '600' - 110 1047 '417' 0.026 134.5 857 '359' 0.058 150 768 '300' - 300 384 '180' - 600 192 'OCO' - 1200 96 '060' - 1800 64 '040' - 2000 58 '03A' 0.69 2400 48 '030' - 3600 32 '020' - 4800 24 '018' - 7200 16 '010' - 9600 12 'OOC' - ~ Line Status Register This 8-bit register provides status information to the CPU concerning the data transfer. The contents ofthe Line Status Register are indicated and described below. Line Status Register (LSR) 3FD BIT 6 4 3 2 1 0 DATA READY (DR) OVERRUN ERROR (OR) I Li=: PARITY ERROR (PE) ... FRAMING ERROR (FE) !: :. BREAK INTERRUPT (BI) TRANSMITTER HOLDING REGISTER EMPTY (TH RE) ... po TX SHIFT REGISTER EMPTY (TSRE) =0 - 2-137
Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1 whenever a complete incoming character has been received and transferred into the Receiver Buffer Register. Bit 0 may be reset to a logic 0 either by the CPU reading the data in the Receiver Buffer Register or by writing a logic 0 into it from the CPU. Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1 indicates that r--... data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby destroying the previous character. The OE indicator is reset whenever the CPU reads the contents of the Line Status Register. Bit 2: This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity-select bit. the PE bit is set to a logic 1 upon detection of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. Bit 3:This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a valid Stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is held in the Spacing (logic 0) state r--... for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any of the corresponding conditions are detected. Bit 5: This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the INS8250 is ready to accept a new character for transmission. In addition, this bit causes the INS8250 to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set high. The THRE bit is set to a logic 1 when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic 0 concurrently with the loading of the Transmitter Holding Register by the CPU. Bit 6: This bit is the Transmitter Shift Register Empty (TSRE) indicator. Bit 6 is set to a logic 1 whenever the Transmitter Shift Register is idle. It is reset to logic 0 upon a data transfer from the Tranmitter Holding Register to the Transmitter Shift Register. Bit 6 is a read-only bit. Bit 7: This bit is permanently set to logic O. 2-138
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April 2011 IMPORTANT 1. The motherb
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FEDERAL COMMUNICATIONS COMMISSION R
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CONTENTS SECTION 1. HARDWARE OVERV
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Programming Considerations ........
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INS 8250 Functional Pin Description
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FIGURE LISTING 1. System Block Dia
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SECTION I. HARDWARE OVERVIEW The
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The 16KB Memory Expansion Kits allo
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SECTION 2. HARDWARE ~ Contents: Sys
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SYSTEM BOARD The System Board fits
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The memory is dynamic 16K x 1 chips
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System Board Data Flow Figure 2. S
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1/0 Channel Diagram REAR PANEl SI
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I/O CHRDY I I/O Channel Ready: This
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System Board Component Diagram REA
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Keyboard Interface B lock Diagram
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Cassette User Interface The cassett
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Cassette Interface Connector Specif
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I/O Address Map HEX RANGE 9 8 7 6
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System Memory Map X'OOOOO' 16 TO 6
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System Memory Map Cont. START ADDR
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5-1/4" Diskette Drives Switch Setti
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32/64KB Memory Expansion Option Sw
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Power Supply The system DC power su
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N I ~ VI ) § I • \. ~ o el so.
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IBM Monochrome Display and Parallel
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System Channel Interface Lines Used
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Programming Considerations Programm
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• CRT Status Port (I/O Address '3
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Color/Graphics Monitor Adapter The
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CPU .. r-- ) ) ) DISPLAY ADDRESS BU
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Modes of Operation There are two ba
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IBM Monochrome Display Adapter V s.
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Color selection is determined by th
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1"'"""""\ Table 5. I R G B Summary
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Programming the Mode Control and St
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Bit 5 When on, this bit will change
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I/O Address and Bit Map Read/Write
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Color/Graphics Monitor Adapter Auxi
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Parallel Printer Adapter The Printe
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Programming Considerations The Prin
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Parallel Printer Adapter Interface
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Table 7. Printer Specifications (1
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Table 9. Functions and Conditions o
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Table 10. Connector Pin Assignment
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(4) Data transfer sequence Fig. 17
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ASCII Control Codes Control Codes V
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(8) DC 2 (Device Control 2) The DC
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(b) 3) ESC 2 (Escape 2) Receipt of
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ehaves like the LF code. Therefore,
Page 106 and 107: [DATA] IESCGI ABCDEFGHI [PRINT] ABC
Page 108 and 109: 5 1/4-Inch Diskette Drive Adapter T
Page 110 and 111: ~ Functional Description From a pro
Page 112 and 113: The FOe is capable of performing 15
Page 114 and 115: Table 13. Symbol Descriptions (cont
Page 116 and 117: Command Summary (continued) DATA B
Page 118 and 119: Command Summary (continued) DATA B
Page 120 and 121: Table 15. Status Register I BIT NO.
Page 122 and 123: Table 17. Status Register 3 BIT NO.
Page 124 and 125: ~ ~ +AO-9 +AEN -lOW -lOR -DACK2 +T
Page 126 and 127: Adapter Inputs -Index -Write Protec
Page 128 and 129: 5-1/4" Diskette Drive Adapter Exter
Page 130 and 131: (3) The write-protect sensor disabl
Page 132 and 133: Memory Expansion Options Two Memory
Page 134 and 135: Switch - Configurable Start Address
Page 136 and 137: Game Control Adapter The Game Co
Page 138 and 139: I/O Channel Description A9-AO: D7-D
Page 140 and 141: ) ) ) 15 PIN MALE '0' SHELL c....t
Page 142 and 143: Asynchronous Communications Adapter
Page 144 and 145: Modes of Operation The different mo
Page 146 and 147: I TRANSMIT 'IACUIT I +5V ~ 4S-"l Tx
Page 148 and 149: INS8250 Functional Pin Description
Page 150 and 151: Data Set Ready (DSR), Pin 37: When
Page 152 and 153: Input/Output Signals Data (D7-DO) B
Page 154 and 155: Bit 3: This bit is the Parity Enabl
Page 158 and 159: Interrupt Identification Register T
Page 160 and 161: Interrupt Enable Register This 8-bi
Page 162 and 163: In the diagnostic mode, the receive
Page 164 and 165: Transmitter Holding Register The T
Page 166 and 167: Asynchronous Communications Adapter
Page 168 and 169: SECTION 3. ROM and SYSTEM r", USAGE
Page 170 and 171: MOV AH,l ;function is to set time o
Page 172 and 173: Vectors With Special Meanings Inter
Page 174 and 175: BIOS Memory Map STARTING ADDRESS H
Page 176 and 177: The timer is set mode 3 which means
Page 178 and 179: Keyboard Encoding and Usage Encodin
Page 180 and 181: Keys 71-83 have meaning only in bas
Page 182 and 183: ALT - Temporarily shifts keys 2-13,
Page 184 and 185: Keyboard Usage This section is inte
Page 186 and 187: Table 28. BASIC Screen Editor Speci
Page 188 and 189: Low Memory Maps (O-'0600'x) Table 3
Page 190 and 191: BASIC Workspace Variables If you do
Page 192: APPENDICES Contents: Appendix A: RO
Page 195 and 196: lOC OBJ LINE SOURCE STITlE( ROM BIO
Page 197 and 198: LOC OBJ LINE SOURCE 0068 ?! 155 De
Page 199 and 200: LOC OBJ LINE SOURCE E09E BBf5 EOAO
Page 201 and 202: lOC OBJ LINE SOURCE £179 E2FD 462
Page 203 and 204: LOC OBJ LINE SOURCE E278 7408 612 J
Page 205 and 206: lOC OBJ LINE SOURCE 755 ; ---------
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LOC OSJ LINE SOU RCE E42B 7440 900
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lOC OBJ LINE SOURCE ESIE 884000 E52
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LaC OBJ LINE SOURCE E613 803E120001
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LaC OSJ LINE SOURCE E6EC eSOAOE E6E
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LaC OBJ LINE SOURCE E7SF 1505 .402:
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LaC OBJ LINE SOURCE 1659 ASSUME CS:
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LOC OBJ LINE SOURCE E994 8E08 1798
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LOC 08J LINE SOURCE £"91 474849 EA
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LaC OBJ LINE SOURCE E890 E99700 E89
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LOC 08J LINE SOURCE 2255 ;-- INT 13
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LOC OS! LINE SOURCE 2407 ;------ DI
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lOC OBJ LINE SOURCE (Eol 7438 fE03
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LOC OBJ LINE SOURCE Ef'tD £67200 2
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LOC OBJ LINE SOURCE 2870 I ~- -----
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LOC (lBJ LINE SOURCE 3007 j --- INT
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laC OBJ LINE SOURCE 3157 (AH}=6 SCR
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lOC OBJ LINE SOURt.:E FOA43828ZDOAI
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lOC OBJ LINE SOURCE FtC7 3458 VIDEO
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LOC OBJ LINE SOURCE F260 750E f2:62
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LOC OBJ LINE SOURCE F32B 06 3760 PU
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LOC OBJ LINE SOURCE F3Cl 3910 NEAR
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laC OBJ LINE SOURCE 1'460 80HfE F46
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LOC OBJ LINE SOURCE F4FF BSFB 4213
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LOC OBJ LINE SOURCE 4359 j------ IM
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LOC OBJ LINE SOURCE F689 57 4511 PU
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lOC OBJ LINE SOLIRCE 4662 THE 0 COL
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LOC OBJ LINE SOURCE F7Cl 8AC4 F7e]
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LaC OBJ LINE SOURCE F840 4967 EQUIP
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LOC OBJ LINE SOURCE F8DA E304 5116
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LOC OBJ LINE SOURCE F97E EBF9 5268
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LOC OBJ LINE SOURCE H20 C3 5415 RET
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LOC OBJ LINE SOURCE fC46 0030300000
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LOC OBJ LINE SOURCE FEBS 833E6E0018
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lOC OBJ LINE SOURCE 5866 ;.*.-•
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A-82 NOTES
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8088 REGISTER MODEL AX: AH Al ACCUM
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MEMORY SEGMENTATION MODEL LOGICAL
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XCHG =Exchange RegisterImemory with
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SBB = Subtract with borrow Reg./mem
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AND = And Reg./memory and register
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Indirect within segment 11111111 mo
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8088 CONDITIONAL TRANSFER OPERATION
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BOBBINSTRUCTION SET MATRIX LO HI 0
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INSTRUCTION SET INDEX Mnemonic Pag
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VALUE AS CHARACTERS AS TEXT ATTRIBU
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Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
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Character Set (OO-7F) Quick Referen
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C-14 NOTES
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SYSTEM BOARD (PROCESSOR AND SUPPORT
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SYSTEM BOARD (DEVICE DECODES) I~ i
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SYSTEM BOARD (ROS AND BUS DRIVER) ~
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Ṉ-0 SYSTEM BOARD (DYNAMIC MEMORY
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SYSTEM BOARD (KEYBOARD/SENSE/CONTRO
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\:j I " m < -tv CI:I Q » :11:1 Q P
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I- z ..... 0 t:::I 0 ... ;:; ~ r
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tl I-0'1 ," r-" "~ (S"T" 'RESET I E
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~ ~ ~ ~ ~~ IBM MONOCHROME DISPLAY A
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tj III ~ N 14L.517') ~ 0 __________
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~ N s: N CI CO J ~ CI 2 A Y 18 n DA
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IBM MONOCHROME OISPLAY DANGER HAZAR
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COLOR/GRAPHICS MONITOR ADAPTER ~
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1'. -- COLOR/GRAPHICS MONITOR ADAPT
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1 COLOR/GRAPHICS MONITOR ADAPTER :;
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PARALLEL PRINTER ADAPTER D-34
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t:l +AEN AND U'I GATE , ., + ENABL
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t:! W CI CHARGE PUMP 00 AOI en U ~I
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5%" DISKETTE DRIVE .., CI -N ... ';
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t:j ~ N o W z N ;:1'1: ~ aZKO: ." R
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32KB MEMORY EXPANSION d-w- I NNO) 3
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64 ~~ MEMORY EXPANSION ~~ D-46
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BO~ t::l azq +';V[)( +'>vOC 'f c+o;
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D-50 NOTES
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IBM Monochrome Display Size: Length
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12. Binary: (1) Pertaining to a sel
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40. Hertz (Hz.): A unit offrequency
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70. OR: A logic operator having the
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G-8 NOTES
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Other Related Publications 7. NATIO
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Asynchronous Communications Adapter
Page 373 and 374:
Character Codes 3-11 Generator 2-
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DIN (Connectors) 2-5 DIP (Dual In-L
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Game Control Adapter (continued) C
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I/O (Input/Output) Address Map 2-33
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Microsecond 2-3 Mnemonic B-18 Mod
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Parameters, 6845 Initialization 2-4
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Read/Write Memory (continued) Grap
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s Scan Codes 2-17 Screen 2-43 Sche
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u Unit Specifications Appendix E
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1-22 NOTES
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III"I UNITED NO POSTAGE NECESSARY
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IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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