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IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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BIOS Cassette Logic<br />

Software Algorithms<br />

Interrupt 15<br />

The cassette routine will be called with the request type in AH and ~<br />

the address of the bytes to be read or written will be specified by <br />

(ES):(BX) and the number of bytes to read/write will be specified by <br />

(CX). The actual number of bytes read will be returned in (DX). <br />

Read block and write block will automatically tum the motor on at the <br />

start and off at the end. The requests are as follows: <br />

(AH) = 0 Tum the cassette motor on. <br />

(AH) = 1<br />

(AH) = 2<br />

(AH) = 3<br />

STATUS:<br />

AH=OO<br />

AH=Ol<br />

AH=02<br />

AH=04<br />

AH=80<br />

Note:<br />

Cassette Write<br />

Tum the cassette motor off. <br />

(Read Block ) Read (CX) bytes into <br />

memory beginning at address (ES):(BX)<br />

and return actual number of bytes read in<br />

(DX). Return the cassette status in (AH).<br />

(Write Block) Write (CX) bytes onto the <br />

cassette beginning at address (DS):(BX). <br />

Return the cassette status in (AH). <br />

No errors<br />

CRC-Error (Read Block)<br />

No data transitions<br />

No leader<br />

Invalid command<br />

The carry flag will be set on any error.<br />

The WRITE BLOCK routine writes a tape block on the cassette. The <br />

tape block is described in Data Record Architecture page (3-10). <br />

The WRITE BLOCK routine turns on the cassette motor and a syn­<br />

chronization bit (0) and then writes 256 bytes of all ones, the leader, <br />

to the tape. Next, one or more data blocks are written (depends on <br />

number in CX). After each data block of 256 bytes, a two byte <br />

CRC is written. The data bytes are taken from the memory location <br />

pointed at by ES. <br />

The WRITE BYTE routine disassembles the byte and writes it a <br />

bit at a time to the cassette. The method used is to set TIMER 2 to <br />

the period of the desired data bit. The timer is set to a period of <br />

1.0 millisecond for a one bit and 0.5 millisecond for a zero bit.<br />

3-8

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