IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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1/0 Channel Diagram REAR PANEl SIGNAL NAME - - 1\ SIGN AL NAME GND - -81 Al- ~ -I/O CH CK +RESET DRV +07 +5V - - +06 +IRU2 r- - +05 -5VDC '- +04 +ORU2 ' - +03 -12V I- +02 RESERVED I- +01 +12V '- +00 GND I- 810 Al0- +1/0 CH ROY -MEMW I- +AEN -MEMR I- +A19 -lOW I- - +A18 -lOR f- +A17 -DACK3 f- +A16 +ORU3 '- - +A15 - - -DACKl ~ - +A14 +ORUl I- +A13 -OACKO f- +A12 CLOCK I- 820 A20 - +All +IRQ7 f- +Al0 +IRQ6 ~ - +AS - +IRQ5 ~ - +A8 +IRQ4 I- +A7 f- +IRQ3 +A6 -DACK2 ~ - +A5 +T/C f- - +A4 +ALE- ~ +A3 +5V I- +A2 +OSC ~ +Al +GNO I- 831 A31 - +AO L....- L..- NOTE: A description of each signal is on the following pages. '\ \ COMPONENT SIDE - Figure 3. I/O CHANNEL DIAGRAM 2-9
System Board I/O Channel Description The following is a description of the <strong>IBM</strong> Personal Computer System Board I/O Channel. All signal lines are TTL compatible. Signal I/O Description OSC 0 Oscillator: This signal is a high speed clock r"\ with a 70 nsec. period (14.31818 MHz.) It hat a 50% duty cycle. CLK 0 Clock: This is the system clock. It is a divide by - three of the oscillator and has a period of 210 nsec. (4.77 Mhz.) The clock has a 33% duty cycle. RESET DRV AO-AI9 o Reset Driver: This line is used to reset or initialize system logic upon power-up or during a low line voltage outage. This signal is synchronized to the falling edge of clock and is active HIGH. o Address Bits 0 to 19: These lines are used to address memory and I/O devices within the system. The 20 address lines allow access ofup to 1 megabyte of memory. AO is the Least Significant Bit (LSB) while A19 is the Most r"\ Significant Bit (MSB). These lines are generated by either the processor or the DMA Controller. They are active HIGH. DO-D7 I/O Data Bits 0 to 7: These lines provide data bus bits 0 to 7 for the processor, memory, and I/O Devices. DO is the Least Significant Bit (LSB) and D7 is the Most Significant Bit (MSB). These lines are active HIGH. ALE o Address Latch Enable: This is provided by the 8288 Bus Controller and is used on the System Board to latch valid addresses from the processor. It is available to the I/O Channel as an indicator of a valid processor address (When used in conjunction with AEN). Processor addresses are latched with the falling edge of ALE. I/O CH CK I -I/O Channei Check: This line provides the CPU with parity (error) information on memory or devices in the I/O Channel. When this signal is active LOW, a parity error is indicated. 2-10 r"\
Page 1: April 2011 IMPORTANT 1. The motherb
Page 5 and 6: FEDERAL COMMUNICATIONS COMMISSION R
Page 8 and 9: CONTENTS SECTION 1. HARDWARE OVERV
Page 10 and 11: Programming Considerations ........
Page 12 and 13: INS 8250 Functional Pin Description
Page 14 and 15: FIGURE LISTING 1. System Block Dia
Page 16 and 17: SECTION I. HARDWARE OVERVIEW The
Page 18 and 19: The 16KB Memory Expansion Kits allo
Page 20 and 21: SECTION 2. HARDWARE ~ Contents: Sys
Page 22 and 23: SYSTEM BOARD The System Board fits
Page 24 and 25: The memory is dynamic 16K x 1 chips
Page 26 and 27: System Board Data Flow Figure 2. S
Page 30 and 31: I/O CHRDY I I/O Channel Ready: This
Page 32 and 33: System Board Component Diagram REA
Page 34 and 35: Keyboard Interface B lock Diagram
Page 36 and 37: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Page 38 and 39: Cassette User Interface The cassett
Page 40 and 41: Cassette Interface Connector Specif
Page 42 and 43: I/O Address Map HEX RANGE 9 8 7 6
Page 44 and 45: System Memory Map X'OOOOO' 16 TO 6
Page 46 and 47: System Memory Map Cont. START ADDR
Page 48 and 49: 5-1/4" Diskette Drives Switch Setti
Page 50 and 51: 32/64KB Memory Expansion Option Sw
Page 52 and 53: Power Supply The system DC power su
Page 54 and 55: N I ~ VI ) § I • \. ~ o el so.
Page 56 and 57: IBM Monochrome Display and Parallel
Page 58 and 59: System Channel Interface Lines Used
Page 60 and 61: Programming Considerations Programm
Page 62 and 63: • CRT Status Port (I/O Address '3
Page 64 and 65: Color/Graphics Monitor Adapter The
Page 66 and 67: CPU .. r-- ) ) ) DISPLAY ADDRESS BU
Page 68 and 69: Modes of Operation There are two ba
Page 70 and 71: IBM Monochrome Display Adapter V s.
Page 72 and 73: Color selection is determined by th
Page 74 and 75: 1"'"""""\ Table 5. I R G B Summary
Page 76 and 77: Programming the Mode Control and St
Page 78 and 79:
Bit 5 When on, this bit will change
Page 80 and 81:
I/O Address and Bit Map Read/Write
Page 82 and 83:
Color/Graphics Monitor Adapter Auxi
Page 84 and 85:
Parallel Printer Adapter The Printe
Page 86 and 87:
Programming Considerations The Prin
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Parallel Printer Adapter Interface
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Table 7. Printer Specifications (1
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Table 9. Functions and Conditions o
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Table 10. Connector Pin Assignment
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(4) Data transfer sequence Fig. 17
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ASCII Control Codes Control Codes V
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(8) DC 2 (Device Control 2) The DC
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(b) 3) ESC 2 (Escape 2) Receipt of
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ehaves like the LF code. Therefore,
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[DATA] IESCGI ABCDEFGHI [PRINT] ABC
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5 1/4-Inch Diskette Drive Adapter T
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~ Functional Description From a pro
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The FOe is capable of performing 15
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Table 13. Symbol Descriptions (cont
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Command Summary (continued) DATA B
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Command Summary (continued) DATA B
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Table 15. Status Register I BIT NO.
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Table 17. Status Register 3 BIT NO.
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~ ~ +AO-9 +AEN -lOW -lOR -DACK2 +T
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Adapter Inputs -Index -Write Protec
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5-1/4" Diskette Drive Adapter Exter
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(3) The write-protect sensor disabl
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Memory Expansion Options Two Memory
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Switch - Configurable Start Address
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Game Control Adapter The Game Co
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I/O Channel Description A9-AO: D7-D
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) ) ) 15 PIN MALE '0' SHELL c....t
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Asynchronous Communications Adapter
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Modes of Operation The different mo
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I TRANSMIT 'IACUIT I +5V ~ 4S-"l Tx
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INS8250 Functional Pin Description
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Data Set Ready (DSR), Pin 37: When
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Input/Output Signals Data (D7-DO) B
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Bit 3: This bit is the Parity Enabl
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Table 23. BAUD RATE AT 1.843 Mhz De
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Interrupt Identification Register T
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Interrupt Enable Register This 8-bi
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In the diagnostic mode, the receive
Page 164 and 165:
Transmitter Holding Register The T
Page 166 and 167:
Page 168 and 169:
SECTION 3. ROM and SYSTEM r", USAGE
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MOV AH,l ;function is to set time o
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Vectors With Special Meanings Inter
Page 174 and 175:
BIOS Memory Map STARTING ADDRESS H
Page 176 and 177:
The timer is set mode 3 which means
Page 178 and 179:
Keyboard Encoding and Usage Encodin
Page 180 and 181:
Keys 71-83 have meaning only in bas
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ALT - Temporarily shifts keys 2-13,
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Keyboard Usage This section is inte
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Table 28. BASIC Screen Editor Speci
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Low Memory Maps (O-'0600'x) Table 3
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BASIC Workspace Variables If you do
Page 192:
APPENDICES Contents: Appendix A: RO
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lOC OBJ LINE SOURCE STITlE( ROM BIO
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LOC OBJ LINE SOURCE 0068 ?! 155 De
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LOC OBJ LINE SOURCE E09E BBf5 EOAO
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lOC OBJ LINE SOURCE £179 E2FD 462
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LOC OBJ LINE SOURCE E278 7408 612 J
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lOC OBJ LINE SOURCE 755 ; ---------
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LOC OSJ LINE SOU RCE E42B 7440 900
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lOC OBJ LINE SOURCE ESIE 884000 E52
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LaC OBJ LINE SOURCE E613 803E120001
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LaC OSJ LINE SOURCE E6EC eSOAOE E6E
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LaC OBJ LINE SOURCE E7SF 1505 .402:
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LaC OBJ LINE SOURCE 1659 ASSUME CS:
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LOC OBJ LINE SOURCE E994 8E08 1798
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LOC 08J LINE SOURCE £"91 474849 EA
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LaC OBJ LINE SOURCE E890 E99700 E89
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LOC 08J LINE SOURCE 2255 ;-- INT 13
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LOC OS! LINE SOURCE 2407 ;------ DI
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lOC OBJ LINE SOURCE (Eol 7438 fE03
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LOC OBJ LINE SOURCE Ef'tD £67200 2
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LOC OBJ LINE SOURCE 2870 I ~- -----
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LOC (lBJ LINE SOURCE 3007 j --- INT
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laC OBJ LINE SOURCE 3157 (AH}=6 SCR
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lOC OBJ LINE SOURt.:E FOA43828ZDOAI
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lOC OBJ LINE SOURCE FtC7 3458 VIDEO
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LOC OBJ LINE SOURCE F260 750E f2:62
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LOC OBJ LINE SOURCE F32B 06 3760 PU
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LOC OBJ LINE SOURCE F3Cl 3910 NEAR
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laC OBJ LINE SOURCE 1'460 80HfE F46
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LOC OBJ LINE SOURCE F4FF BSFB 4213
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LOC OBJ LINE SOURCE 4359 j------ IM
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LOC OBJ LINE SOURCE F689 57 4511 PU
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lOC OBJ LINE SOLIRCE 4662 THE 0 COL
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LOC OBJ LINE SOURCE F7Cl 8AC4 F7e]
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LaC OBJ LINE SOURCE F840 4967 EQUIP
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LOC OBJ LINE SOURCE F8DA E304 5116
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LOC OBJ LINE SOURCE F97E EBF9 5268
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LOC OBJ LINE SOURCE H20 C3 5415 RET
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LOC OBJ LINE SOURCE fC46 0030300000
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LOC OBJ LINE SOURCE FEBS 833E6E0018
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lOC OBJ LINE SOURCE 5866 ;.*.-•
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A-82 NOTES
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8088 REGISTER MODEL AX: AH Al ACCUM
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MEMORY SEGMENTATION MODEL LOGICAL
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XCHG =Exchange RegisterImemory with
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SBB = Subtract with borrow Reg./mem
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AND = And Reg./memory and register
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Indirect within segment 11111111 mo
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8088 CONDITIONAL TRANSFER OPERATION
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BOBBINSTRUCTION SET MATRIX LO HI 0
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INSTRUCTION SET INDEX Mnemonic Pag
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VALUE AS CHARACTERS AS TEXT ATTRIBU
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Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Character Set (OO-7F) Quick Referen
Page 307 and 308:
C-14 NOTES
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SYSTEM BOARD (PROCESSOR AND SUPPORT
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SYSTEM BOARD (DEVICE DECODES) I~ i
Page 313 and 314:
SYSTEM BOARD (ROS AND BUS DRIVER) ~
Page 315 and 316:
Ṉ-0 SYSTEM BOARD (DYNAMIC MEMORY
Page 317 and 318:
SYSTEM BOARD (KEYBOARD/SENSE/CONTRO
Page 319 and 320:
\:j I " m < -tv CI:I Q » :11:1 Q P
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I- z ..... 0 t:::I 0 ... ;:; ~ r
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tl I-0'1 ," r-" "~ (S"T" 'RESET I E
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~ ~ ~ ~ ~~ IBM MONOCHROME DISPLAY A
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tj III ~ N 14L.517') ~ 0 __________
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~ N s: N CI CO J ~ CI 2 A Y 18 n DA
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IBM MONOCHROME OISPLAY DANGER HAZAR
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COLOR/GRAPHICS MONITOR ADAPTER ~
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1'. -- COLOR/GRAPHICS MONITOR ADAPT
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1 COLOR/GRAPHICS MONITOR ADAPTER :;
Page 341 and 342:
PARALLEL PRINTER ADAPTER D-34
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t:l +AEN AND U'I GATE , ., + ENABL
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t:! W CI CHARGE PUMP 00 AOI en U ~I
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5%" DISKETTE DRIVE .., CI -N ... ';
Page 349 and 350:
t:j ~ N o W z N ;:1'1: ~ aZKO: ." R
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32KB MEMORY EXPANSION d-w- I NNO) 3
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64 ~~ MEMORY EXPANSION ~~ D-46
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BO~ t::l azq +';V[)( +'>vOC 'f c+o;
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D-50 NOTES
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IBM Monochrome Display Size: Length
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12. Binary: (1) Pertaining to a sel
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40. Hertz (Hz.): A unit offrequency
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70. OR: A logic operator having the
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G-8 NOTES
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Other Related Publications 7. NATIO
Page 371 and 372:
Page 373 and 374:
Character Codes 3-11 Generator 2-
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DIN (Connectors) 2-5 DIP (Dual In-L
Page 377 and 378:
Game Control Adapter (continued) C
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I/O (Input/Output) Address Map 2-33
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Microsecond 2-3 Mnemonic B-18 Mod
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Parameters, 6845 Initialization 2-4
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Read/Write Memory (continued) Grap
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s Scan Codes 2-17 Screen 2-43 Sche
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u Unit Specifications Appendix E
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1-22 NOTES
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III"I UNITED NO POSTAGE NECESSARY
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IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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