IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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MOV = Move Register/memory to/ from register DATA TRANSFER 11 0 0 0 1 0 d w I mod reg rIm Immediate to register/memory 1 1 0 0 0 1 1 w mod 0 0 0 rIm data data if w=l Immediate to register 1 0 1 1 w reg data data if w=l Memory to accumulator 101 0 0 0 0 w addr-Iow addr-high Accumulator to memory 1010001w addr-Iow addr-high Register/memory to segment register 11 0 0 0 1 1 1 0 I mod 0 reg rim Segment register to register/memory 11 0 0 0 1 1 0 0 mod 0 reg rIm PUSH = Push Register/memory 11 1 1 1 1 1 1 1 mod 1 1 0 rim Register 0 1 0 1 0 reg Segment register I0 0 0 reg 1 0 r---... POP =Pop Register/memory 1 0 0 0 1 1 1 Register 1 0 1 0 1 1 reg 1 mod 0 0 0 rim Segment register 10 0 0 reg 1 1 B-S
XCHG =Exchange RegisterImemory with register 11 0 0 0 0 1 1 w 1 mod reg rIm Register with accumulator 110010regl IN = Input to AL/AX from Fixed port 11 1 1 0 0 1 0 w port Variable port (OX) 11110110W OUT =Output from ALIAX to Fixed port 11 1 1 0 0 1 1 w port Variable port (OX) 11 1 10111w XLAT =Translate byte to AL 1110101111 LEA =Load EA to register I 1 0 0 0 1 1 0 1 I mod reg rIm LDS =Load pointer to OS 11 1 0 0 0 1 0 1 mod reg rIm LES =Load pointer to ES 11 1 0 0 0 1 0 0 mod reg rIm LAHF =Load AH with flags 1100111111 SAHF =Store AH into flags 1100111101 PUSHF = Push flags 110011100 POPF = Pop flags 110011101 B-6
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April 2011 IMPORTANT 1. The motherb
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FEDERAL COMMUNICATIONS COMMISSION R
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CONTENTS SECTION 1. HARDWARE OVERV
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Programming Considerations ........
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INS 8250 Functional Pin Description
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FIGURE LISTING 1. System Block Dia
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SECTION I. HARDWARE OVERVIEW The
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The 16KB Memory Expansion Kits allo
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SECTION 2. HARDWARE ~ Contents: Sys
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SYSTEM BOARD The System Board fits
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The memory is dynamic 16K x 1 chips
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System Board Data Flow Figure 2. S
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1/0 Channel Diagram REAR PANEl SI
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I/O CHRDY I I/O Channel Ready: This
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System Board Component Diagram REA
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Keyboard Interface B lock Diagram
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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Cassette User Interface The cassett
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Cassette Interface Connector Specif
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I/O Address Map HEX RANGE 9 8 7 6
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System Memory Map X'OOOOO' 16 TO 6
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System Memory Map Cont. START ADDR
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5-1/4" Diskette Drives Switch Setti
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32/64KB Memory Expansion Option Sw
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Power Supply The system DC power su
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N I ~ VI ) § I • \. ~ o el so.
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IBM Monochrome Display and Parallel
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System Channel Interface Lines Used
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Programming Considerations Programm
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• CRT Status Port (I/O Address '3
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Color/Graphics Monitor Adapter The
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CPU .. r-- ) ) ) DISPLAY ADDRESS BU
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Modes of Operation There are two ba
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IBM Monochrome Display Adapter V s.
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Color selection is determined by th
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1"'"""""\ Table 5. I R G B Summary
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Programming the Mode Control and St
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Bit 5 When on, this bit will change
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I/O Address and Bit Map Read/Write
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Color/Graphics Monitor Adapter Auxi
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Parallel Printer Adapter The Printe
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Programming Considerations The Prin
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Parallel Printer Adapter Interface
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Table 7. Printer Specifications (1
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Table 9. Functions and Conditions o
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Table 10. Connector Pin Assignment
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(4) Data transfer sequence Fig. 17
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ASCII Control Codes Control Codes V
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(8) DC 2 (Device Control 2) The DC
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(b) 3) ESC 2 (Escape 2) Receipt of
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ehaves like the LF code. Therefore,
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[DATA] IESCGI ABCDEFGHI [PRINT] ABC
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5 1/4-Inch Diskette Drive Adapter T
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~ Functional Description From a pro
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The FOe is capable of performing 15
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Table 13. Symbol Descriptions (cont
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Command Summary (continued) DATA B
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Command Summary (continued) DATA B
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Table 15. Status Register I BIT NO.
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Table 17. Status Register 3 BIT NO.
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~ ~ +AO-9 +AEN -lOW -lOR -DACK2 +T
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Adapter Inputs -Index -Write Protec
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5-1/4" Diskette Drive Adapter Exter
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(3) The write-protect sensor disabl
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Memory Expansion Options Two Memory
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Switch - Configurable Start Address
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Game Control Adapter The Game Co
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I/O Channel Description A9-AO: D7-D
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) ) ) 15 PIN MALE '0' SHELL c....t
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Asynchronous Communications Adapter
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Modes of Operation The different mo
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I TRANSMIT 'IACUIT I +5V ~ 4S-"l Tx
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INS8250 Functional Pin Description
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Data Set Ready (DSR), Pin 37: When
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Input/Output Signals Data (D7-DO) B
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Bit 3: This bit is the Parity Enabl
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Table 23. BAUD RATE AT 1.843 Mhz De
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Interrupt Identification Register T
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Interrupt Enable Register This 8-bi
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In the diagnostic mode, the receive
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Transmitter Holding Register The T
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SECTION 3. ROM and SYSTEM r", USAGE
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MOV AH,l ;function is to set time o
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Vectors With Special Meanings Inter
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BIOS Memory Map STARTING ADDRESS H
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The timer is set mode 3 which means
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Keyboard Encoding and Usage Encodin
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Keys 71-83 have meaning only in bas
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ALT - Temporarily shifts keys 2-13,
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Keyboard Usage This section is inte
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Table 28. BASIC Screen Editor Speci
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Low Memory Maps (O-'0600'x) Table 3
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BASIC Workspace Variables If you do
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APPENDICES Contents: Appendix A: RO
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lOC OBJ LINE SOURCE STITlE( ROM BIO
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LOC OBJ LINE SOURCE 0068 ?! 155 De
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LOC OBJ LINE SOURCE E09E BBf5 EOAO
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lOC OBJ LINE SOURCE £179 E2FD 462
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LOC OBJ LINE SOURCE E278 7408 612 J
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lOC OBJ LINE SOURCE 755 ; ---------
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LOC OSJ LINE SOU RCE E42B 7440 900
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lOC OBJ LINE SOURCE ESIE 884000 E52
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LaC OBJ LINE SOURCE E613 803E120001
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LaC OSJ LINE SOURCE E6EC eSOAOE E6E
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LaC OBJ LINE SOURCE E7SF 1505 .402:
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LaC OBJ LINE SOURCE 1659 ASSUME CS:
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LOC OBJ LINE SOURCE E994 8E08 1798
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LOC 08J LINE SOURCE £"91 474849 EA
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LaC OBJ LINE SOURCE E890 E99700 E89
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LOC 08J LINE SOURCE 2255 ;-- INT 13
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LOC OS! LINE SOURCE 2407 ;------ DI
Page 229 and 230: lOC OBJ LINE SOURCE (Eol 7438 fE03
Page 231 and 232: LOC OBJ LINE SOURCE Ef'tD £67200 2
Page 233 and 234: LOC OBJ LINE SOURCE 2870 I ~- -----
Page 235 and 236: LOC (lBJ LINE SOURCE 3007 j --- INT
Page 237 and 238: laC OBJ LINE SOURCE 3157 (AH}=6 SCR
Page 239 and 240: lOC OBJ LINE SOURt.:E FOA43828ZDOAI
Page 241 and 242: lOC OBJ LINE SOURCE FtC7 3458 VIDEO
Page 243 and 244: LOC OBJ LINE SOURCE F260 750E f2:62
Page 245 and 246: LOC OBJ LINE SOURCE F32B 06 3760 PU
Page 247 and 248: LOC OBJ LINE SOURCE F3Cl 3910 NEAR
Page 249 and 250: laC OBJ LINE SOURCE 1'460 80HfE F46
Page 251 and 252: LOC OBJ LINE SOURCE F4FF BSFB 4213
Page 253 and 254: LOC OBJ LINE SOURCE 4359 j------ IM
Page 255 and 256: LOC OBJ LINE SOURCE F689 57 4511 PU
Page 257 and 258: lOC OBJ LINE SOLIRCE 4662 THE 0 COL
Page 259 and 260: LOC OBJ LINE SOURCE F7Cl 8AC4 F7e]
Page 261 and 262: LaC OBJ LINE SOURCE F840 4967 EQUIP
Page 263 and 264: LOC OBJ LINE SOURCE F8DA E304 5116
Page 265 and 266: LOC OBJ LINE SOURCE F97E EBF9 5268
Page 267 and 268: LOC OBJ LINE SOURCE H20 C3 5415 RET
Page 269 and 270: LOC OBJ LINE SOURCE fC46 0030300000
Page 271 and 272: LOC OBJ LINE SOURCE FEBS 833E6E0018
Page 273 and 274: lOC OBJ LINE SOURCE 5866 ;.*.-•
Page 275 and 276: A-82 NOTES
Page 277 and 278: 8088 REGISTER MODEL AX: AH Al ACCUM
Page 279: MEMORY SEGMENTATION MODEL LOGICAL
Page 283 and 284: SBB = Subtract with borrow Reg./mem
Page 285 and 286: AND = And Reg./memory and register
Page 287 and 288: Indirect within segment 11111111 mo
Page 289 and 290: 8088 CONDITIONAL TRANSFER OPERATION
Page 291 and 292: BOBBINSTRUCTION SET MATRIX LO HI 0
Page 293 and 294: INSTRUCTION SET INDEX Mnemonic Pag
Page 295 and 296: VALUE AS CHARACTERS AS TEXT ATTRIBU
Page 305 and 306: Character Set (OO-7F) Quick Referen
Page 307 and 308: C-14 NOTES
Page 309 and 310: SYSTEM BOARD (PROCESSOR AND SUPPORT
Page 311 and 312: SYSTEM BOARD (DEVICE DECODES) I~ i
Page 313 and 314: SYSTEM BOARD (ROS AND BUS DRIVER) ~
Page 315 and 316: Ṉ-0 SYSTEM BOARD (DYNAMIC MEMORY
Page 317 and 318: SYSTEM BOARD (KEYBOARD/SENSE/CONTRO
Page 319 and 320: \:j I " m < -tv CI:I Q » :11:1 Q P
Page 321 and 322: I- z ..... 0 t:::I 0 ... ;:; ~ r
Page 323 and 324: tl I-0'1 ," r-" "~ (S"T" 'RESET I E
Page 325 and 326: ~ ~ ~ ~ ~~ IBM MONOCHROME DISPLAY A
Page 327 and 328: tj III ~ N 14L.517') ~ 0 __________
Page 329 and 330: ~ N s: N CI CO J ~ CI 2 A Y 18 n DA
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IBM MONOCHROME OISPLAY DANGER HAZAR
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COLOR/GRAPHICS MONITOR ADAPTER ~
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1'. -- COLOR/GRAPHICS MONITOR ADAPT
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1 COLOR/GRAPHICS MONITOR ADAPTER :;
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PARALLEL PRINTER ADAPTER D-34
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t:l +AEN AND U'I GATE , ., + ENABL
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t:! W CI CHARGE PUMP 00 AOI en U ~I
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5%" DISKETTE DRIVE .., CI -N ... ';
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t:j ~ N o W z N ;:1'1: ~ aZKO: ." R
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32KB MEMORY EXPANSION d-w- I NNO) 3
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64 ~~ MEMORY EXPANSION ~~ D-46
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BO~ t::l azq +';V[)( +'>vOC 'f c+o;
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D-50 NOTES
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IBM Monochrome Display Size: Length
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12. Binary: (1) Pertaining to a sel
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40. Hertz (Hz.): A unit offrequency
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70. OR: A logic operator having the
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G-8 NOTES
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Other Related Publications 7. NATIO
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Character Codes 3-11 Generator 2-
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DIN (Connectors) 2-5 DIP (Dual In-L
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Game Control Adapter (continued) C
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I/O (Input/Output) Address Map 2-33
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Microsecond 2-3 Mnemonic B-18 Mod
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Parameters, 6845 Initialization 2-4
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Read/Write Memory (continued) Grap
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s Scan Codes 2-17 Screen 2-43 Sche
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u Unit Specifications Appendix E
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1-22 NOTES
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III"I UNITED NO POSTAGE NECESSARY
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IBM 5150 PC Technical Reference (6025005, August, 1981) (PDF)

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