TheTTL - Al Kossow's Bitsavers

· TIFPLA839, TIFPLA840
14 x 32 x 6 FIELD·PROGRAMMABLE LOGIC ARRAYS
Step 5:
Step 6:
Step 7:
Step 8:
Step 9:
Step 10:
Step 11:
Verify
PROGRAMMING PROCEDURE
Lower the voltage on the first input to VIH for a true. or to VIL for the complement.
After td. raise PGM ENABLE to VIHH.
After additional td. pulse the PGM input to VIH for two
After additional td delay. lower PGM ENABLE to VILL.
Disable programmed input by raising it back to VIH.
Repeat steps 5 through 9 for each input.
Repeat steps 4 through 10 for each product term.
Step 1:
Step 2:
Step 3:
Step 4:
Step 5:
Set PGM ENABLE (pin 1) to VILL; set Vee (pin 24) to Vee3.
Enable PO output by setting PGM to VIX.
Disable all inputs by applying VIX to the I inputs.
Address the product term to be verified (0 through 31) by applying its binary code on outputs'PAO through
PA4.
Lower the input voltage on the first input to VIH and check the logic level of output PO. then lower the
same input to VIL and again check the level of PO. The input variable state contained in the product term
is determined from the following table. Two tests are required to verify the programmed state of each variable.
Step 6:
Step 7:
Step 8:
STATE
TRUE
COMPLEMENT
DON'T CARE
INACTIVE
Disable verified input by raising it back to VIX.
Repeat steps 5 and 6 for all other inputs.
Repeat steps 4 through 7 for all other product terms.
tr~
0
tdH
PGMENABlE ________ I-T-----~~~~~~~ ::::
I
L
H
L
H
L
H
L
H
: td~tW~~ ________ VIX
____ ~-:::..--~I I I __ VIH
~H I I .
PGM
~
--------VIX
----.J
-------- VIH
PIO THRU PI13
~ : : : -------- Vil
~td I . ro---"'1 • I I V
All PA PINS f%J: I: -- IH
I I I -- Vil
--------~I~-------------~I-_T~~Ir_------VOH
All PO PINS
PO
L
H
H
L
H
H
L
L
I@
-------~I~------------------~.~~~~.~-------VOl
\+--- PROGRAM ----.+_1 •• --"_I VERIFY
FIGURE 2. AND MATRIX PROGRAMMING WAVEFORMS
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INSTRUMENTS
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