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TBP38S165, TBP38S166, TBP38S16X 16,384·BIT (2048 WORDS BY 8·BITS) STANDARD PROGRAMMABLE READ·ONLY MEMORY WITH 3·STATE OUTPUTS recommended operating conditions for programming (see Figure 1) Supply voltage during verification Input voltage Enable voltage during verification Enable inactive voltage during programming VCC program pulse amplitude VCC program pulse duration Enable set-up time T before VCC(pr) Enable hold timet after VCC(pr) Rise time of VCC(pr) § 11 st attempt I 2nd attempt 13rd attempt Fall time of VCc(pr) 1 Delay time between successive VCC(pr) pulses Delay time between successive VCC(pr) pulses Cooling time between words Free-air temperature tMeasured from 1.5 V on enable pin to 5.5 V on VCC(pr) +Measured from 5.5 V on VCC(pr) to 1.5 V on enable pin §Measured from 5 V to 12 V 1Measured from 12 V to 5 V MIN VCC 4.5 VIH 3 VIL 0 G1 0 G2, G3 3 G1 4.5 G2, G3 0 VCC(pr) 12 tw1 10 tw2 20 tw3 20 tsu(en) 0.1 th(en) 0.1 tr(VCC) 0.3 tf(VCC) 0.05 td1 10 td2 10 tcool 100 TA 20 NOM MAX UNIT 5 5.5 V 4 5 0.2 0.5 0.2 0.4 4 5 5 5.5 0.2 0.4 V V V 12,5 13 V 11 12 22 25 p'S 22 25 0.5 1 Jls 0.5 1 Jls 0.4 0.5 Jls . 0.1 0.2 Jls 20 30 Jls 20 30 Jls 150 200 JlS 25 30 °c step-by-step programming instructions (see Figure 1) 1. Address the word to be programmed, apply 5 volts to Vee and active levels to all enable inputs (G1, G2,G3). 2. Verify the selected bit location that requires programming. Note: The only bit positions that require programming are outputs needing a high logic level. 3. For bit locations that do not require programming, go to step 2 for the next bit, or to step 1 for next word. 4. Deselect PROM by applying 5 volts to G1, or 0 volts to G2 or G3. 5. Connect a 4-mA current source (clamped to Vee) to the output that is to be programmed. 6. Increase Vee to Vee(pr) for a pulse duration equal to twx (where X is determined by the number of programming attempts, i.e., 1,2,3). Minimum current capability for the Vee power supply should be 400 mAo 7. Verify that the output has been programmed to a high logic level. If the output has been programmed correctly, go to the next bit. If not, repeat step 2 through step 7 and increment X (where X is equal to 1 on the first programming attempt). If the output has not been programmed by the third attempt, stop programming and go to a new device. S. Verify programming of every word after all words have been programmed using Vee values of 4.5 volts and 5.5 volts. U) ~ o a:: 0. TEXAS .. INSTRUMENTS POST OFFICE BOX 225012 • DALLAS. TEXAS 75265 4-91
TBP38S165, TBP38S166, TBP38S16X 16,384-BIT (2048 WORDS BY 8 BITS) STANDARD PROGRAMMABLE READ-ONLY MEMORY WITH 3-STATE OUTPUTS AOTO A10J VALID ADDRESS : Vee G I !4-I1-tw1 ~tw2 I4--tt-tw3 , , I , , I ,t It 01 , I' I 02 I I 07 I I ~ j4-th(enl I I 1 I I ~ I x= I4"*-tw1 , I ------ 12.5V PROGRAM 02 ~ } ~ ~I PROGRAM 07 I -----5V OV - VOH L VOL L - VOH VOL VOH VOL Illustrated above is the following sequence: 1) It is desired to program the selected address with 01100001 (00-071. Only outputs 01, 02 and 07 need programming. 21 01 is verified to be at a low logic level and then the programming sequence is executed. The output is then verified to be at a high logic level. 31 02 is an example of an output requiring three attempts to be programmed successfully. 41 07 is programmed to a high logic level. FIGURE 1. SERIES 3 PROGRAMMING SEQUENCE 4-92 TEXAS. INSTRUMENTS POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
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SDZD001B TheTTL ,Data Book Volume 4
Page 4:
General Information Functional Inde
Page 7 and 8:
IMPORTANT NOTICE Texas Instruments
Page 9 and 10:
G) CD ::::s CD ... ~ ::::s ..... o
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A new Field Programmable Logic Appl
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ALPHANUMERIC INDEX RAMs and Memory-
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GLOSSARY Output-Enable Input A gati
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GLOSSARY C) CD :::J CD ... ~ .... 5
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EXPLANATION OF FUNCTION TABLES The
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SERIES 1 AND 2 PROMs, RAMs, MEMORY
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SERIES TIBPAL', PAL', TIFPLA DEVICE
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ORDERING INFORMATION II PROM NUMBER
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::J -o 3 Q) .-+ o· ::J 1-20
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HARDWARE/SOFTWARE MANUFACTURERS ADD
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'T1 c: ::J n ... o· ::J ~ ::J Q, C
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FUNCTIONAL Ir~DEX GATES, EXPANDERS,
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FUNCTIONAL INDEX BUFFERS, DRIVERS,
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FUNCTIONAL INDEX LATCHES AND MUL TI
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FUNCTIONAL INDEX COUNTERS II "T1 r:
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FUNCTIONAL INDEX DISPLAY DECODERS/D
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FUNCTIONAL INDEX ARITHMETIC CIRCUIT
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FUNCTIONAL INDEX PROGRAMMABLE LOGIC
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"T1 m· c: ." ""I o cc ""I Q) 3 3 Q
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PAL16R4A, PAL16R6A, PAL16R8A STANDA
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PAL 16R6A, PAL 16R8A STANDARD HIGH
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~ PAL16R4A STANDARD HIGH,SPEED PAL
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PAL16RBA STANDARD HIGH·SPEED PAL C
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PAL 16L8A, PAL 16R4A, PAL 16R6A, PA
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PAL 16L8A, PAL 16R4A, PAL 16R6A, PA
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3-16
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PAL20R4A. PAL20R6A. PAL20R8A STANDA
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PAL20R6A. PAL20R8A STANDARD HIGH SP
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PAL20R4A STANDARD HIGH SPEED PAL CI
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PAL20R8A STANDARD HIGH SPEED PAL CI
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PAL20L8A, PAL20R4A, PAL20R6A, PAL20
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TIBPAL 16R4, TIBPAL 16R6, TIBPAL 16
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TIBPAL 16R6, TIBPAL 16R8 HIGH·PERF
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TIBPAL16R4 HIGH·PERFORMANCE IMPACT
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TIBPAL 16R8 HIGH·PERFORMANCE IMPAC
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TIBPAL 16LH, TIBPAL 16R4, TIBPAL 16
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TIBPAL 16L8, TIBPAL 16R4, TIBPAL 16
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"T1 [ Co ""I o cc ""I Q) 3 3 Q) C"
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TIBPAL 16R4·12, TIBPAL 16R6·12, T
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TIBPAL 16R6·12, TIBPAL 16R8·12 12
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~ TIBPAL 16R4·12 12·NS IMPAcr M P
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~ TIBPAL 16R8,12 12,NS IMPACr M PAL
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TIBPAL 16L8·12, TIBPAL 16R4·12, T
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TIBPAL 16L8·12, TIBPAL 16R4·12, T
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"T1 [ Co I ""0 ... o cc ... D.l 3 3
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THCTPAL16L8, THCTPAL16R4, THCTPAL16
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TIBPAL20R4·15, TIBPAL20R6·15, TIB
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TIBPAL20R6·15, TIBPAL20R8·15 TIBP
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'"T1 (1). e: ... -a o cc ... Q) 3 3
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TIBPAL20R8·15 TIBPAL20R8·20 HIGH
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TIBPAL20L8·15, TIBPAL20R4·15, TIB
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TIBPAL20L8·15, TIBPAL20R4·15, TIB
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TIBPAL20X4, TIBPAL20X8, TIBPAL20X10
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TIBPAL20X8, TIBPAL20X10 HIGH·PERFO
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~ TIBPAL20X4 HIGH·PERFORMANCE EXCL
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TIBPAL20X10 HIGH·PERFORMANCE EXCLU
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TIBPAL20L 10, TIBPAL20X4, TIBPAL20X
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TlBPAL20L 10, TIBPAL20X4, TlBPAL20X
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TIBPALR19R4, TIBPALR19R6, TIBPALR19
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TIBPALR19R6, TIBPALR19R8 HIGH·PERF
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TIBPALR19R4 HIGH·PERFORMANCE REGIS
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TIBPALR 19R8 HIGH-PERFORMANCE REGIS
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TIBPALR19L8, TIBPALR19R4, TIBPALR19
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TIBPALR19L8, TIBPALR19R4, TlBPALR19
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TIBPALT19R4, TIBPALT19R6, TIBPALT19
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TIBPALT19R6, TIBPALT19R8 HIGH·PERF
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TIBPAL T1 9R4 HIGH·PERFORMANCE LAT
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TIBPALT19RB HIGH·PERFORMANCE LATCH
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TIBPALT19L8. TIBPAL T19R4. TIBPAL T
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TIBPALT19L8, TIBPALT19R4, TIBPALT19
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TIBPAL T19L8. TIBPALT19R4. TIBPALT1
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TIBPALT19L8, TIBPALT19R4, TIBPALT19
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TIB82S105B 16 x 48 x 8 FIELD·PROGR
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TIB82S1058 16 x 48 x 8 FIELD·PROGR
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TIB82S167B 14 >< 48 x 6 FIELD·PROG
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TIB82S167B 14 X 48 X 6 FIELD·PROGR
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TIB82S167B 14 x 48 x 6 FIELD-PROGRA
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." [ 9- "'C ~ o CC ~ Q) 3 3 Q) C" m
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." (ii' c: ... -c o cc ... Q) 3 3 Q
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TIFPGA529 FIELD·PROGRAMMABLE GATE
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TIFPLA839. TIFPLA840 14 x 32 x 6 FI
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TIFPLA839, TIFPLA840 14 x 32 x 6 FI
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82S105A 16 x 48 X 8 FIELD·PROGRAMM
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-n m' e: .!a ... o cc ... Q) 3 3 Q)
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82S105A 16 x 48 x 8 FIELD·PROGRAMM
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82S105A . 16 x 48 x 8 FIELD·PROGRA
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82S167A 14 x 48x 6 FIELD·PROGRAMMA
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82S167A 14 X 48 X 6 FIELD·PROGRAMM
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82S167A 14 x 48 x 6 FIELD-PROGRAMMA
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"T1 ~ c. .!g ... o cc ... Q) 3 3 Q)
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." ::JJ o S en 4-2
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BIPOLAR PROM CROSS·REFERENCE GUIDE
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TBP18S030, TBP18SA030 256 BITS (32
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TBP18S030 256 BITS (32 WORDS BY 8 B
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4-10
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SERIES 24 AND 28 STANDARD AND LOW·
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TBP24SA10 1024 BITS (256 WORDS BY 4
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TBP24SA41 4096 BITS (1024 WORDS BY
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TBP24SA81 8192 BITS (2048 WORDS BY
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TBP28SA86A 8192 BITS (1024 WORDS BY
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TBP28S166 16,384 BITS (2084 WORDS B
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TBP28LA22 2048 BITS (256 WORDS BY 8
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TBP28L46 4096 BITS (512 WORDS BY 8
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TBP28L166 16,384 BITS (2084 WORDS B
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SERIES 24 AND 28 PROGRAMMABLE READ
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34R162, TBP34R16X 16,384-BIT (40
Page 275 and 276: TBP34R162, TBP34R16X 16,384-BIT (40
Page 277 and 278: TBP34S10, TBP34L10, TBP34SA10 TBP34
Page 279 and 280: II "tJ :D o S C/) TBP34L10, TBP34L1
Page 281 and 282: TBP34S10, TBP34L10, TBP34A10 TBP34S
Page 283 and 284: "'C ::c o S en 4-48
Page 285 and 286: TBP34S162, TBP34L162, TBP34SA162 TB
Page 287 and 288: II "tJ jJ o s: C/) TBP34L162, TBP34
Page 291 and 292: II 4-56
Page 293 and 294: TBP34SR165, TBP34SR16X 16,384·BIT
Page 295 and 296: TBP34SR165, TBP34SR16X 16,384·811
Page 305 and 306: TBP38L030, TBP38L03X 256·BIT (32 W
Page 309 and 310: "'C :c o s: (J) 4-74
Page 311 and 312: TBP38S8, TBP38L8, TBP38SA8 8,192·B
Page 313 and 314: TBP38L165, TBP38L166, TBP38L16X 16,
Page 319 and 320: TBP38R165, TBP38R16X 16,384-BI1 (20
Page 321 and 322: TBP38R165, TBP38R16X 16,384·BIT (2
Page 323 and 324: 11 "'C :c o S UI TBP38R165, TBP38R1
Page 325: TBP38S165, TBP38S166, TBP38S16X 16,
Page 329 and 330: II 4-94
Page 331 and 332: TBP38SA165, TBP38SA166, TBP38SA16X
Page 333 and 334: TBP38SA165. TBP38SA166. TBP38SA16X
Page 335 and 336: "'C :0 o S rJ) 4-100
Page 339 and 340: TBP38S22, TBP38S2X 2,048-BIT (256 W
Page 341 and 342: TBP38SA22, TBP38SA2X 2,048·BI1 (25
Page 345 and 346: 5-2
Page 347 and 348: SN7489 64·BIT RANDOM·ACCESS READ/
Page 353 and 354: SN54184, SN74184 BCD·TO·BINARY AN
Page 355 and 356: SN54184,SN54185A, SN74184, SN74185A
Page 357 and 358: SN54184, SN74184 BCD·TO·BINARY CO
Page 359 and 360: SN54185, SN74185A BCD·TO·BINARY C
Page 361 and 362: 5-18
Page 363 and 364: SN54LS189A. SN54LS219A. SN54LS289A.
Page 365 and 366: SN54LS189A, SN54LS219A, SN74LS189A,
Page 367 and 368: 5-24
Page 369 and 370: SN54S1890, SN54S2890, SN74S1890, SN
Page 371 and 372: SN54S189B, SN54S289B, SN74S189B, SN
Page 373 and 374: SN74S201, SN74S301 256·811 HIGH·P
Page 375 and 376: SN74S201, SN74S301 256·811 HIGH·P
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SN54284, SN54285, SN74274, SN74285
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SN54284, SN54285, SN74284, SN74285
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SN54S484A, SN54S485A, SN74S484A, SN
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SN54S484A, SN54S485A, SN74S484A, SN
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SN54S484A, SN74S484A BCD·TO·BINAR
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SN54S484A, SN54S485A,SN74S484A, SN7
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SN54S485A. SN74S485A BCD·TO·BINAR
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SN54S485A, SN74S485A BCD-lO-BINARY
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SN54S485A, SN74S485A BCD·IO·BINAR
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5-56
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6-2
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IMPORTANT NOTICE Texas Instruments
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List of Illustrations Figure 1 2 3
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FAMILY ARCHITECTURES As stated befo
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~ ~ ~ INPUT LINES RODUCT, . LINES 0
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ENABLE .10 INPUTS o In PO o o D--+-
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'LS253 'LS162 PAL SELECTION SELO SE
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lEI [e111 It is important to notice
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~ ~ » 'C "2- ri' Q) .... ClK (1) ~
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0000 0000 0011 1111 1111 2222 2222
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modulQ BO_80UNT flao /-r2/ titl~ '4
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ADDRESS FOR PROGRAMMING AND SOFTWAR
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7-2
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MECHANICAL DATA OW plastic "small o
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MECHANICAL DATA FN plastic chip car
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MECHANICAL DATA J ceramic dual-in-l
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MECHANICAL DATA J ceramic dual-in-l
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MECHANICAL DATA N plastic dual-in-l
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MECHANICAL DATA N plastic dual-in-l
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MECHANICAL DATA N plastic dual-in-I
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TI Worldwide Sales Offices ALABAMA:
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