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To overcome the limitation of a restricted number of inputs, the PAL utilizes a slightly different architecture as shown in Figure 4. The same AND-OR implementation is used as with PROMs, but now the input AND array is programmable instead of the output OR array. This has the effect of restricting the output OR array to a fixed number of input AND terms. The trade-off is that now, every output is not programmable from every input combination, but more inputs can be added without doubling the size of the fuse matrix. For example, If we were to expand the inputs on the PAL shown in Figure 4, to 10, and on the PROM in Figure 3, to 10. We would see that the fuse matrix required for the PAL would be 20 x 16 (320 fuses) vs 4 x 1024 (4096 fuses for the PROM). It is important to realize that not every application requires every output be programmable from every input combination. This is what makes the PAL a viable product family. The FPLA goes one step further in offering both a programmable AND array, and a programmable OR array (Figure 5). This feature makes the FPLA the most o c B A "OR" ARRAY (PROGRAMMABLE) .... ~ \ I 9YY9 V "AND" ARRAY (PROGRAMMABLE) r-"\ P< J=< I" '=< ==< =< =< =< =< =< ~ F=< ?< ~ ~ 1/ ~ I-..J Figure 5. FPLA Architecture versatile device of the three, but usually impractical in most low complexity applications. <strong>Al</strong>l three field-programmable logic approaches discussed have their own unique advantages and limitations. The best choice depends on the complexity of the function being implemented and the current cost of the devices themselves. It is important to realize, that a circuit solution may exist from more than one of these logic families. PAL OPTIONS Figure 6 shows the logic diagram of the popular TIBPAL16L8. Its basic architecture is the same as discussed in the previous section, but with the addition of some special circuit features. First notice that the PAL has 10 simple inputs. In addition, 6 of the outputs operate as I/O ports. This allows feedback into the AND array. One AND gate in each product term controls each 3-state output. The architecture used in this PAL makes it very useful in generating all sorts of combinational logic. Another important feature about the logic diagram, and all other block diagrams supplied from individual datasheets, are that there are no X's marked at every fuse location. From the previous convention; we stated that everywhere there was a intact fuse, there was an X . However, in order to make the logic diagram useful when generating specific functions, it is supplied with no X's. This allows the user to insert the X's wherever an intact fuse is desired: The basic concept of the TIBPALl6L8 can be expanded further to include D-type flip-flops on the outputs. An example of this is shown in Figure 7 with the TIBPAL16R8. This added feature allows the device to be configured as a counter, simple storage register, or similar clocked function. Circuit variations which are available on other members of the TI PAL and FPLA family are explained below. Polarity Fuse The polarity of the output can be selected via the fuse shown in Figure 8. Input Registers On PALs equipped with this special feature, the option of having D-type input registers is fuse programmable. Figure 9 shows an example of this type of input. If the fuse is left intact, data enters on a low-high transition of the clock. If the fuse is blown, the register becomes permanently transparent and is equivalent to a normal input buffer. Input Latches On PALs equipped with this special feature, the option of having input latches is fuse programmable. en t: o .,t:; CO .2 C. c. « 6-9
~ ~ ~ INPUT LINES RODUCT, . LINES 0 4 8 12 16 20 24 28 31 ,....... 0 1-
Page 1 and 2:
SDZD001B TheTTL ,Data Book Volume 4
Page 4:
General Information Functional Inde
Page 7 and 8:
IMPORTANT NOTICE Texas Instruments
Page 9 and 10:
G) CD ::::s CD ... ~ ::::s ..... o
Page 11 and 12:
A new Field Programmable Logic Appl
Page 13 and 14:
ALPHANUMERIC INDEX RAMs and Memory-
Page 15 and 16:
GLOSSARY Output-Enable Input A gati
Page 17 and 18:
GLOSSARY C) CD :::J CD ... ~ .... 5
Page 19 and 20:
EXPLANATION OF FUNCTION TABLES The
Page 21 and 22:
SERIES 1 AND 2 PROMs, RAMs, MEMORY
Page 23 and 24:
SERIES TIBPAL', PAL', TIFPLA DEVICE
Page 25 and 26:
ORDERING INFORMATION II PROM NUMBER
Page 27 and 28:
::J -o 3 Q) .-+ o· ::J 1-20
Page 29 and 30:
HARDWARE/SOFTWARE MANUFACTURERS ADD
Page 31 and 32:
'T1 c: ::J n ... o· ::J ~ ::J Q, C
Page 33 and 34:
FUNCTIONAL Ir~DEX GATES, EXPANDERS,
Page 35 and 36:
FUNCTIONAL INDEX BUFFERS, DRIVERS,
Page 37 and 38:
FUNCTIONAL INDEX LATCHES AND MUL TI
Page 39 and 40:
FUNCTIONAL INDEX COUNTERS II "T1 r:
Page 41 and 42:
FUNCTIONAL INDEX DISPLAY DECODERS/D
Page 43 and 44:
FUNCTIONAL INDEX ARITHMETIC CIRCUIT
Page 45 and 46:
FUNCTIONAL INDEX PROGRAMMABLE LOGIC
Page 47 and 48:
"T1 m· c: ." ""I o cc ""I Q) 3 3 Q
Page 49 and 50:
PAL16R4A, PAL16R6A, PAL16R8A STANDA
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PAL 16R6A, PAL 16R8A STANDARD HIGH
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~ PAL16R4A STANDARD HIGH,SPEED PAL
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PAL16RBA STANDARD HIGH·SPEED PAL C
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PAL 16L8A, PAL 16R4A, PAL 16R6A, PA
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PAL 16L8A, PAL 16R4A, PAL 16R6A, PA
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3-16
Page 63 and 64:
PAL20R4A. PAL20R6A. PAL20R8A STANDA
Page 65 and 66:
PAL20R6A. PAL20R8A STANDARD HIGH SP
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PAL20R4A STANDARD HIGH SPEED PAL CI
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PAL20R8A STANDARD HIGH SPEED PAL CI
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PAL20L8A, PAL20R4A, PAL20R6A, PAL20
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Page 75 and 76:
Page 77 and 78:
TIBPAL 16R4, TIBPAL 16R6, TIBPAL 16
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TIBPAL 16R6, TIBPAL 16R8 HIGH·PERF
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TIBPAL16R4 HIGH·PERFORMANCE IMPACT
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TIBPAL 16R8 HIGH·PERFORMANCE IMPAC
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TIBPAL 16LH, TIBPAL 16R4, TIBPAL 16
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TIBPAL 16L8, TIBPAL 16R4, TIBPAL 16
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"T1 [ Co ""I o cc ""I Q) 3 3 Q) C"
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TIBPAL 16R4·12, TIBPAL 16R6·12, T
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TIBPAL 16R6·12, TIBPAL 16R8·12 12
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~ TIBPAL 16R4·12 12·NS IMPAcr M P
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~ TIBPAL 16R8,12 12,NS IMPACr M PAL
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TIBPAL 16L8·12, TIBPAL 16R4·12, T
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TIBPAL 16L8·12, TIBPAL 16R4·12, T
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"T1 [ Co I ""0 ... o cc ... D.l 3 3
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THCTPAL16L8, THCTPAL16R4, THCTPAL16
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TIBPAL20R4·15, TIBPAL20R6·15, TIB
Page 109 and 110:
TIBPAL20R6·15, TIBPAL20R8·15 TIBP
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'"T1 (1). e: ... -a o cc ... Q) 3 3
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TIBPAL20R8·15 TIBPAL20R8·20 HIGH
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TIBPAL20L8·15, TIBPAL20R4·15, TIB
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TIBPAL20L8·15, TIBPAL20R4·15, TIB
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TIBPAL20X4, TIBPAL20X8, TIBPAL20X10
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TIBPAL20X8, TIBPAL20X10 HIGH·PERFO
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~ TIBPAL20X4 HIGH·PERFORMANCE EXCL
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TIBPAL20X10 HIGH·PERFORMANCE EXCLU
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TIBPAL20L 10, TIBPAL20X4, TIBPAL20X
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Page 131 and 132:
TlBPAL20L 10, TIBPAL20X4, TlBPAL20X
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Page 135 and 136:
TIBPALR19R4, TIBPALR19R6, TIBPALR19
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TIBPALR19R6, TIBPALR19R8 HIGH·PERF
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TIBPALR19R4 HIGH·PERFORMANCE REGIS
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TIBPALR 19R8 HIGH-PERFORMANCE REGIS
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TIBPALR19L8, TIBPALR19R4, TIBPALR19
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Page 147 and 148:
Page 149 and 150:
TIBPALR19L8, TIBPALR19R4, TlBPALR19
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TIBPALT19R4, TIBPALT19R6, TIBPALT19
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TIBPALT19R6, TIBPALT19R8 HIGH·PERF
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TIBPAL T1 9R4 HIGH·PERFORMANCE LAT
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TIBPALT19RB HIGH·PERFORMANCE LATCH
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TIBPALT19L8. TIBPAL T19R4. TIBPAL T
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TIBPALT19L8, TIBPALT19R4, TIBPALT19
Page 163 and 164:
TIBPAL T19L8. TIBPALT19R4. TIBPALT1
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TIBPALT19L8, TIBPALT19R4, TIBPALT19
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TIB82S105B 16 x 48 x 8 FIELD·PROGR
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Page 171 and 172:
Page 173 and 174:
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TIB82S1058 16 x 48 x 8 FIELD·PROGR
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Page 181 and 182:
TIB82S167B 14 >< 48 x 6 FIELD·PROG
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Page 185 and 186:
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TIB82S167B 14 X 48 X 6 FIELD·PROGR
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TIB82S167B 14 x 48 x 6 FIELD-PROGRA
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." [ 9- "'C ~ o CC ~ Q) 3 3 Q) C" m
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." (ii' c: ... -c o cc ... Q) 3 3 Q
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TIFPGA529 FIELD·PROGRAMMABLE GATE
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Page 201 and 202:
Page 203 and 204:
TIFPLA839. TIFPLA840 14 x 32 x 6 FI
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TIFPLA839, TIFPLA840 14 x 32 x 6 FI
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Page 209 and 210:
Page 211 and 212:
82S105A 16 x 48 X 8 FIELD·PROGRAMM
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-n m' e: .!a ... o cc ... Q) 3 3 Q)
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82S105A 16 x 48 x 8 FIELD·PROGRAMM
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82S105A . 16 x 48 x 8 FIELD·PROGRA
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Page 223 and 224:
82S167A 14 x 48x 6 FIELD·PROGRAMMA
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Page 229 and 230:
82S167A 14 X 48 X 6 FIELD·PROGRAMM
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82S167A 14 x 48 x 6 FIELD-PROGRAMMA
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Page 235 and 236:
"T1 ~ c. .!g ... o cc ... Q) 3 3 Q)
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." ::JJ o S en 4-2
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BIPOLAR PROM CROSS·REFERENCE GUIDE
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TBP18S030, TBP18SA030 256 BITS (32
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TBP18S030 256 BITS (32 WORDS BY 8 B
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4-10
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SERIES 24 AND 28 STANDARD AND LOW·
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TBP24SA10 1024 BITS (256 WORDS BY 4
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Page 253 and 254:
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TBP24SA41 4096 BITS (1024 WORDS BY
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TBP24SA81 8192 BITS (2048 WORDS BY
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TBP28SA86A 8192 BITS (1024 WORDS BY
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TBP28S166 16,384 BITS (2084 WORDS B
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TBP28LA22 2048 BITS (256 WORDS BY 8
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TBP28L46 4096 BITS (512 WORDS BY 8
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TBP28L166 16,384 BITS (2084 WORDS B
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SERIES 24 AND 28 PROGRAMMABLE READ
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34S10, TBP34L10, TBP34SA10 TBP34
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II "tJ :D o S C/) TBP34L10, TBP34L1
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TBP34S10, TBP34L10, TBP34A10 TBP34S
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"'C ::c o S en 4-48
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TBP34S162, TBP34L162, TBP34SA162 TB
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II "tJ jJ o s: C/) TBP34L162, TBP34
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Page 291 and 292:
II 4-56
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TBP34SR165, TBP34SR16X 16,384·BIT
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TBP34SR165, TBP34SR16X 16,384·811
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Page 301 and 302:
Page 303 and 304:
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TBP38L030, TBP38L03X 256·BIT (32 W
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Page 309 and 310:
"'C :c o s: (J) 4-74
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TBP38S8, TBP38L8, TBP38SA8 8,192·B
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TBP38L165, TBP38L166, TBP38L16X 16,
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TBP38L165, TBP38L166, TBP38L16X 16,
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TBP38L165, TBP38L166, TBP38L16X 16,
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TBP38R165, TBP38R16X 16,384-BI1 (20
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TBP38R165, TBP38R16X 16,384·BIT (2
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11 "'C :c o S UI TBP38R165, TBP38R1
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TBP38S165, TBP38S166, TBP38S16X 16,
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TBP38S165, TBP38S166, TBP38S16X 16,
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II 4-94
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TBP38SA165, TBP38SA166, TBP38SA16X
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TBP38SA165. TBP38SA166. TBP38SA16X
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"'C :0 o S rJ) 4-100
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Page 339 and 340:
TBP38S22, TBP38S2X 2,048-BIT (256 W
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TBP38SA22, TBP38SA2X 2,048·BI1 (25
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Page 345 and 346:
5-2
Page 347 and 348:
SN7489 64·BIT RANDOM·ACCESS READ/
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Page 351 and 352:
Page 353 and 354:
SN54184, SN74184 BCD·TO·BINARY AN
Page 355 and 356:
SN54184,SN54185A, SN74184, SN74185A
Page 357 and 358: SN54184, SN74184 BCD·TO·BINARY CO
Page 359 and 360: SN54185, SN74185A BCD·TO·BINARY C
Page 361 and 362: 5-18
Page 363 and 364: SN54LS189A. SN54LS219A. SN54LS289A.
Page 365 and 366: SN54LS189A, SN54LS219A, SN74LS189A,
Page 367 and 368: 5-24
Page 369 and 370: SN54S1890, SN54S2890, SN74S1890, SN
Page 371 and 372: SN54S189B, SN54S289B, SN74S189B, SN
Page 373 and 374: SN74S201, SN74S301 256·811 HIGH·P
Page 375 and 376: SN74S201, SN74S301 256·811 HIGH·P
Page 377 and 378: SN54284, SN54285, SN74274, SN74285
Page 379 and 380: SN54284, SN54285, SN74284, SN74285
Page 381 and 382: SN54S484A, SN54S485A, SN74S484A, SN
Page 383 and 384: SN54S484A, SN54S485A, SN74S484A, SN
Page 385 and 386: SN54S484A, SN74S484A BCD·TO·BINAR
Page 387 and 388: SN54S484A, SN54S485A,SN74S484A, SN7
Page 391 and 392: SN54S485A. SN74S485A BCD·TO·BINAR
Page 393 and 394: SN54S485A, SN74S485A BCD-lO-BINARY
Page 395 and 396: SN54S485A, SN74S485A BCD·IO·BINAR
Page 399 and 400: 5-56
Page 401 and 402: 6-2
Page 403 and 404: IMPORTANT NOTICE Texas Instruments
Page 405 and 406: List of Illustrations Figure 1 2 3
Page 407: FAMILY ARCHITECTURES As stated befo
Page 411 and 412: ENABLE .10 INPUTS o In PO o o D--+-
Page 413 and 414: 'LS253 'LS162 PAL SELECTION SELO SE
Page 415 and 416: lEI [e111 It is important to notice
Page 417 and 418: ~ ~ » 'C "2- ri' Q) .... ClK (1) ~
Page 419 and 420: 0000 0000 0011 1111 1111 2222 2222
Page 421 and 422: modulQ BO_80UNT flao /-r2/ titl~ '4
Page 423 and 424: ADDRESS FOR PROGRAMMING AND SOFTWAR
Page 425 and 426: 7-2
Page 427 and 428: MECHANICAL DATA OW plastic "small o
Page 429 and 430: MECHANICAL DATA FN plastic chip car
Page 431 and 432: MECHANICAL DATA J ceramic dual-in-l
Page 433 and 434: MECHANICAL DATA J ceramic dual-in-l
Page 435 and 436: MECHANICAL DATA N plastic dual-in-l
Page 437 and 438: MECHANICAL DATA N plastic dual-in-l
Page 439: MECHANICAL DATA N plastic dual-in-I
Page 443: TI Worldwide Sales Offices ALABAMA:
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