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SN54S189B, SN54S289B, SN74S189B, SN74S289B 64·BIT HIGH·PERFORMANCE RANDOM·ACCESS MEMORIES SEPTEMBER 1976-REVISED FEBRUARY 1984 STATIC RANDOM-ACCESS MEMORIES • Fully Decoded RAMs Organized as 16 Words of Four Bits Each • Schottky·Clamped for High Speed: Read Cycle Time ... 25 ns Typical Write Cycle Time ••. 25 ns Typical • Choice of Three~State or Open·Collector Outputs • Compatible with Most TTL and 12L Circuits • Chip-Select Input Simplifies External Decoding SN54S189B. SN54S289B ... J OR W PACKAGE SN74S189B. SN74S289B .•. J OR N PACKAGE (TOP VIEW) AO Vee S <strong>Al</strong> W A2 01 A3 01 04 02 04 02 03 GNO 0.3 description These 64-bit active-element memories are monolithic Schottky-clamped transistor-transistor logic (TTL) arrays organized as 16 words of four bits each. They are fully decoded and feature a chip-select input to simplify decoding required to achieve expanded system organization. The memories feature p-n-p input transistors that reduce the low-level input current requirement to a maximum of - 0.25 milliamperes, only one-eighth that of a Series 54S/74S standard load factor. The chip-select circuitry is implemented with minimal delay times to compensate for added system decoding. write cycle The information applied at the data input is written into the selected location when the chip-select input and the write-enable input are low. While the write-enable input is iow, the'S 189B output is in the highimpedance state and the 'S289B output is off. When a number of outputs are bus-connected, this highimpedance or off state will neither load nor drive the bus line, but it will allow the bus line to be driven by another active output or a passive pull-up. read cycle III The stored information (complement of information applied at the data input during the write cycle) is available at the output when the write-enable input is high and the chip-select input is low. When the chipselect input is high, the 'S189B output will be in the high-impedance state and the 'S289B output will be off. FUNCTION Write Read Inhibit CHIP SELECT L L INPUTS WRITE ENABLE L H X H '" high level. L '" low level. X '" irrelevant H U) FUNCTION TABLE 2: 'S189B OUTPUT High Impedance Complement of Data Entered High Impedance 'S289B OUTPUT Off Complement of Data Entered Off « a: TEXAS .. INSTRUMENTS POST OFFICE BOX 225012 • DALLAS, TEXAS 75265 Copyright © 1979. Texas Instruments Incorporated 5-25
SN54S1890, SN54S2890, SN74S1890, SN74S2890 64·01T HIGH·PERFORMANCE RANDOM·ACCESS MEMORIES logic symbols functional block diagram AO A1 A2 A3 S RNi (1) (15) (14) 'S189B RAM 16X 4 1 EN [READ] 1 C2 [WRITE] AO (1) A2 (14) A3 (13) ADDRESS BUFFERS 1·0F·16 DECODERS 54·BIT MEMORY MATRIX ORGANIZED 16·X-4 01 02 03 04 (10) (12) READIWRITE (RM) (3) AO A1 A2 A3 S R/w 'S289B RAM 16X 4 (7) (9) (11) il1 02 03 04 01 02 (6) 03 (10) (12) 04 schematics of inputs and outputs EaUIVALENT OF EACH INPUT vcc----------~.----e~ 'S189B OUTPUT ..... ------~~---VCC 58 n NOM 'S289B OUTPUT 5-26 TEXAS -1!1 ' INSTRUMENTS POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
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SDZD001B TheTTL ,Data Book Volume 4
Page 4:
General Information Functional Inde
Page 7 and 8:
IMPORTANT NOTICE Texas Instruments
Page 9 and 10:
G) CD ::::s CD ... ~ ::::s ..... o
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A new Field Programmable Logic Appl
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ALPHANUMERIC INDEX RAMs and Memory-
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GLOSSARY Output-Enable Input A gati
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GLOSSARY C) CD :::J CD ... ~ .... 5
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EXPLANATION OF FUNCTION TABLES The
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SERIES 1 AND 2 PROMs, RAMs, MEMORY
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SERIES TIBPAL', PAL', TIFPLA DEVICE
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ORDERING INFORMATION II PROM NUMBER
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::J -o 3 Q) .-+ o· ::J 1-20
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HARDWARE/SOFTWARE MANUFACTURERS ADD
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'T1 c: ::J n ... o· ::J ~ ::J Q, C
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FUNCTIONAL Ir~DEX GATES, EXPANDERS,
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FUNCTIONAL INDEX BUFFERS, DRIVERS,
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FUNCTIONAL INDEX LATCHES AND MUL TI
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FUNCTIONAL INDEX COUNTERS II "T1 r:
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FUNCTIONAL INDEX DISPLAY DECODERS/D
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FUNCTIONAL INDEX ARITHMETIC CIRCUIT
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FUNCTIONAL INDEX PROGRAMMABLE LOGIC
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"T1 m· c: ." ""I o cc ""I Q) 3 3 Q
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PAL16R4A, PAL16R6A, PAL16R8A STANDA
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PAL 16R6A, PAL 16R8A STANDARD HIGH
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~ PAL16R4A STANDARD HIGH,SPEED PAL
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PAL16RBA STANDARD HIGH·SPEED PAL C
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PAL 16L8A, PAL 16R4A, PAL 16R6A, PA
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PAL 16L8A, PAL 16R4A, PAL 16R6A, PA
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3-16
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PAL20R4A. PAL20R6A. PAL20R8A STANDA
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PAL20R6A. PAL20R8A STANDARD HIGH SP
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PAL20R4A STANDARD HIGH SPEED PAL CI
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PAL20R8A STANDARD HIGH SPEED PAL CI
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PAL20L8A, PAL20R4A, PAL20R6A, PAL20
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TIBPAL 16R4, TIBPAL 16R6, TIBPAL 16
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TIBPAL 16R6, TIBPAL 16R8 HIGH·PERF
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TIBPAL16R4 HIGH·PERFORMANCE IMPACT
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TIBPAL 16R8 HIGH·PERFORMANCE IMPAC
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TIBPAL 16LH, TIBPAL 16R4, TIBPAL 16
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TIBPAL 16L8, TIBPAL 16R4, TIBPAL 16
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"T1 [ Co ""I o cc ""I Q) 3 3 Q) C"
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TIBPAL 16R4·12, TIBPAL 16R6·12, T
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TIBPAL 16R6·12, TIBPAL 16R8·12 12
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~ TIBPAL 16R4·12 12·NS IMPAcr M P
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~ TIBPAL 16R8,12 12,NS IMPACr M PAL
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TIBPAL 16L8·12, TIBPAL 16R4·12, T
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TIBPAL 16L8·12, TIBPAL 16R4·12, T
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"T1 [ Co I ""0 ... o cc ... D.l 3 3
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THCTPAL16L8, THCTPAL16R4, THCTPAL16
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TIBPAL20R4·15, TIBPAL20R6·15, TIB
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TIBPAL20R6·15, TIBPAL20R8·15 TIBP
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'"T1 (1). e: ... -a o cc ... Q) 3 3
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TIBPAL20R8·15 TIBPAL20R8·20 HIGH
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TIBPAL20L8·15, TIBPAL20R4·15, TIB
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TIBPAL20L8·15, TIBPAL20R4·15, TIB
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TIBPAL20X4, TIBPAL20X8, TIBPAL20X10
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TIBPAL20X8, TIBPAL20X10 HIGH·PERFO
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~ TIBPAL20X4 HIGH·PERFORMANCE EXCL
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TIBPAL20X10 HIGH·PERFORMANCE EXCLU
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TIBPAL20L 10, TIBPAL20X4, TIBPAL20X
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TlBPAL20L 10, TIBPAL20X4, TlBPAL20X
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TIBPALR19R4, TIBPALR19R6, TIBPALR19
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TIBPALR19R6, TIBPALR19R8 HIGH·PERF
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TIBPALR19R4 HIGH·PERFORMANCE REGIS
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TIBPALR 19R8 HIGH-PERFORMANCE REGIS
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TIBPALR19L8, TIBPALR19R4, TIBPALR19
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TIBPALR19L8, TIBPALR19R4, TlBPALR19
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TIBPALT19R4, TIBPALT19R6, TIBPALT19
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TIBPALT19R6, TIBPALT19R8 HIGH·PERF
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TIBPAL T1 9R4 HIGH·PERFORMANCE LAT
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TIBPALT19RB HIGH·PERFORMANCE LATCH
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TIBPALT19L8. TIBPAL T19R4. TIBPAL T
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TIBPALT19L8, TIBPALT19R4, TIBPALT19
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TIBPAL T19L8. TIBPALT19R4. TIBPALT1
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TIBPALT19L8, TIBPALT19R4, TIBPALT19
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TIB82S105B 16 x 48 x 8 FIELD·PROGR
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TIB82S1058 16 x 48 x 8 FIELD·PROGR
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TIB82S167B 14 >< 48 x 6 FIELD·PROG
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TIB82S167B 14 X 48 X 6 FIELD·PROGR
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TIB82S167B 14 x 48 x 6 FIELD-PROGRA
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." [ 9- "'C ~ o CC ~ Q) 3 3 Q) C" m
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." (ii' c: ... -c o cc ... Q) 3 3 Q
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TIFPGA529 FIELD·PROGRAMMABLE GATE
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TIFPLA839. TIFPLA840 14 x 32 x 6 FI
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TIFPLA839, TIFPLA840 14 x 32 x 6 FI
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82S105A 16 x 48 X 8 FIELD·PROGRAMM
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-n m' e: .!a ... o cc ... Q) 3 3 Q)
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82S105A 16 x 48 x 8 FIELD·PROGRAMM
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82S105A . 16 x 48 x 8 FIELD·PROGRA
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82S167A 14 x 48x 6 FIELD·PROGRAMMA
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82S167A 14 X 48 X 6 FIELD·PROGRAMM
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82S167A 14 x 48 x 6 FIELD-PROGRAMMA
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"T1 ~ c. .!g ... o cc ... Q) 3 3 Q)
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." ::JJ o S en 4-2
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BIPOLAR PROM CROSS·REFERENCE GUIDE
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TBP18S030, TBP18SA030 256 BITS (32
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TBP18S030 256 BITS (32 WORDS BY 8 B
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4-10
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SERIES 24 AND 28 STANDARD AND LOW·
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TBP24SA10 1024 BITS (256 WORDS BY 4
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TBP24SA41 4096 BITS (1024 WORDS BY
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TBP24SA81 8192 BITS (2048 WORDS BY
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TBP28SA86A 8192 BITS (1024 WORDS BY
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TBP28S166 16,384 BITS (2084 WORDS B
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TBP28LA22 2048 BITS (256 WORDS BY 8
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TBP28L46 4096 BITS (512 WORDS BY 8
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TBP28L166 16,384 BITS (2084 WORDS B
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SERIES 24 AND 28 PROGRAMMABLE READ
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34R162, TBP34R16X 16,384-BIT (40
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TBP34S10, TBP34L10, TBP34SA10 TBP34
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II "tJ :D o S C/) TBP34L10, TBP34L1
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TBP34S10, TBP34L10, TBP34A10 TBP34S
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"'C ::c o S en 4-48
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TBP34S162, TBP34L162, TBP34SA162 TB
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II "tJ jJ o s: C/) TBP34L162, TBP34
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II 4-56
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TBP34SR165, TBP34SR16X 16,384·BIT
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TBP34SR165, TBP34SR16X 16,384·811
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TBP38L030, TBP38L03X 256·BIT (32 W
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"'C :c o s: (J) 4-74
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TBP38S8, TBP38L8, TBP38SA8 8,192·B
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TBP38L165, TBP38L166, TBP38L16X 16,
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TBP38L165, TBP38L166, TBP38L16X 16,
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Page 319 and 320: TBP38R165, TBP38R16X 16,384-BI1 (20
Page 321 and 322: TBP38R165, TBP38R16X 16,384·BIT (2
Page 323 and 324: 11 "'C :c o S UI TBP38R165, TBP38R1
Page 325 and 326: TBP38S165, TBP38S166, TBP38S16X 16,
Page 327 and 328: TBP38S165, TBP38S166, TBP38S16X 16,
Page 329 and 330: II 4-94
Page 331 and 332: TBP38SA165, TBP38SA166, TBP38SA16X
Page 333 and 334: TBP38SA165. TBP38SA166. TBP38SA16X
Page 335 and 336: "'C :0 o S rJ) 4-100
Page 337 and 338: TBP38S22, TBP38L22, TBP38SA22 TBP38
Page 339 and 340: TBP38S22, TBP38S2X 2,048-BIT (256 W
Page 341 and 342: TBP38SA22, TBP38SA2X 2,048·BI1 (25
Page 343 and 344: TBP38S22, TBP38L22, TBP38SA22 TBP38
Page 345 and 346: 5-2
Page 347 and 348: SN7489 64·BIT RANDOM·ACCESS READ/
Page 353 and 354: SN54184, SN74184 BCD·TO·BINARY AN
Page 355 and 356: SN54184,SN54185A, SN74184, SN74185A
Page 357 and 358: SN54184, SN74184 BCD·TO·BINARY CO
Page 359 and 360: SN54185, SN74185A BCD·TO·BINARY C
Page 361 and 362: 5-18
Page 363 and 364: SN54LS189A. SN54LS219A. SN54LS289A.
Page 365 and 366: SN54LS189A, SN54LS219A, SN74LS189A,
Page 367: 5-24
Page 371 and 372: SN54S189B, SN54S289B, SN74S189B, SN
Page 373 and 374: SN74S201, SN74S301 256·811 HIGH·P
Page 375 and 376: SN74S201, SN74S301 256·811 HIGH·P
Page 377 and 378: SN54284, SN54285, SN74274, SN74285
Page 379 and 380: SN54284, SN54285, SN74284, SN74285
Page 381 and 382: SN54S484A, SN54S485A, SN74S484A, SN
Page 383 and 384: SN54S484A, SN54S485A, SN74S484A, SN
Page 385 and 386: SN54S484A, SN74S484A BCD·TO·BINAR
Page 387 and 388: SN54S484A, SN54S485A,SN74S484A, SN7
Page 391 and 392: SN54S485A. SN74S485A BCD·TO·BINAR
Page 393 and 394: SN54S485A, SN74S485A BCD-lO-BINARY
Page 395 and 396: SN54S485A, SN74S485A BCD·IO·BINAR
Page 399 and 400: 5-56
Page 401 and 402: 6-2
Page 403 and 404: IMPORTANT NOTICE Texas Instruments
Page 405 and 406: List of Illustrations Figure 1 2 3
Page 407 and 408: FAMILY ARCHITECTURES As stated befo
Page 409 and 410: ~ ~ ~ INPUT LINES RODUCT, . LINES 0
Page 411 and 412: ENABLE .10 INPUTS o In PO o o D--+-
Page 413 and 414: 'LS253 'LS162 PAL SELECTION SELO SE
Page 415 and 416: lEI [e111 It is important to notice
Page 417 and 418: ~ ~ » 'C "2- ri' Q) .... ClK (1) ~
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0000 0000 0011 1111 1111 2222 2222
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modulQ BO_80UNT flao /-r2/ titl~ '4
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ADDRESS FOR PROGRAMMING AND SOFTWAR
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7-2
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MECHANICAL DATA OW plastic "small o
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MECHANICAL DATA FN plastic chip car
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MECHANICAL DATA J ceramic dual-in-l
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MECHANICAL DATA J ceramic dual-in-l
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MECHANICAL DATA N plastic dual-in-l
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MECHANICAL DATA N plastic dual-in-l
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MECHANICAL DATA N plastic dual-in-I
Page 443:
TI Worldwide Sales Offices ALABAMA:
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