Master of Engineering Balram Sahu - Embedded Sensing ...

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3.2. Standard transmission gate CMOS Flip-flop 12degrade the output while passing 0 by its threshold voltage and transmits 1 as it is.Thus we construct the transmission gate by adding an NOMOS device with a PMOStransistor in parallel and controlling their gates by opposite clock levels as shown infigure 3.2.Figure 3.2: Transmission GateAs we have discussed in section 2.2 that I ON to I OF F ratio of transistor degrades in subthresholdregime and OFF current is significantly comparable to ON current, transmissiongates may fail to block the input and can pass a wrong value as shown in Figure 3.3.Figure 3.3: Leakage in transmission Gate3.2 Standard transmission gate CMOS Flip-flopA standard transmission gate CMOS flip-flop two level-sensitive latches, made by usingtransmission gates as shown in figure 3.4.When the clock is low, the first (master) latch output follows the D input while the second(slave) latch holds the previous value. Thus when the clock rises from 0 to 1, the masterlatch become opaque and holds the D value at the time of the clock transition.
13 3.2. Standard transmission gate CMOS Flip-flopFigure 3.4: Standard transmission gate CMOS flip-flopSince Standard transmission gate flip-flop uses transmission gate and transmission gatesare not good to operate in sub-threshold regime, we can not use these flip-flops forthe same operating voltage range. There is a risk of data write-back in these flip-flopsoperating in sub-threshold voltage as shown in figure 3.5.Figure 3.5: Data Write-Back in Standard Transmission Gate Flip-flop.In Figure 3.5, flip-flop is being operated in state S1, i.e. node A is at voltage level 1 andthis state is being hold by feedback loop in slave latch. Similarly node B is at voltagelevel 0 in state S1. But node B can be corrupted by the leakage of transmission gate andmay cross the V IH (Minimum Input High voltage) of feedback inverter in master latch.This will invert the master latch state and in the next positive clock edge wrong datamay be transmitted. This is called as "Data Write-Back".
Page 1: "Minimum Energy Point Operation of
Page 4 and 5: CONTENTSiv4 Flip-Flop Characterizat
Page 6 and 7: LIST OF FIGURESvi5.3 Normalized Del
Page 8 and 9: viii
Page 12 and 13: 1.4. Thesis Organization 4harvestin
Page 14 and 15: 2.1. Modeling for Sub-threshold ope
Page 16 and 17: 2.2. Challenges in Sub-threshold op
Page 18 and 19: 2.2. Challenges in Sub-threshold op
Page 22 and 23: 3.3. Clocked Inverter CMOS Flip-flo
Page 24 and 25: 3.4. Modification in Standard Cell
Page 26 and 27: 4.1. Requirements on the library 18
Page 28 and 29: 4.3. Generation of LEF 20each metal
Page 30 and 31: 4.3. Generation of LEF 2221 PORTLAY
Page 32 and 33: 4.4. Behavioral Model 24127 RECT 3
Page 34 and 35: 4.4. Behavioral Model 26#Falling ed
Page 36 and 37: 4.4. Behavioral Model 28Figure 4.7:
Page 38 and 39: 4.4. Behavioral Model 30v a l u e s
Page 40 and 41: 4.4. Behavioral Model 32
Page 42 and 43: 5.2. Process Flow 34changes and thu
Page 44 and 45: 5.3. Results 365.3 ResultsCORDIC al
Page 46 and 47: 5.4. Comparison of results with Nor
Page 48 and 49: 5.5. The openMSP430 Micro-controlle
Page 50 and 51: 6.2. Scope for Future Work 426.2 Sc
Page 52 and 53: A.1. Input Requirements of SoC Enco
Page 54 and 55: A.2. SoC Encounter Flow 46design hi
Page 56 and 57: A.2. SoC Encounter Flow 48Do the se
Page 58 and 59: A.2. SoC Encounter Flow 50Figure A.
Page 60 and 61: A.2. SoC Encounter Flow 52
Page 62 and 63: 54The first part can be generated b
Page 64 and 65: 563. Press RUN button and wait unti
Page 66: BIBLIOGRAPHY 58[11] FARADAY cell li

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