Master of Engineering Balram Sahu - Embedded Sensing ...

Chapter 6Conclusions And Scope for FutureWork6.1 ConclusionsThis work proposes the implementation of ASIC design operable at sub-threshold voltagesso that the minimum energy point is achievable. We have addressed the issue in subthresholdcircuit design and problems with transmission gates and stacked devices. Forthis, we modified the standard cell library and designed the clocked-inverter flip-flop forthe library. We have used the design of clocked-inverter flip-flop from [8]. The proposedmethodology was applied for an CORDIC algorithm in rotation mode at clock frequencyof 200MHz and successfully able to achieve the minimum energy point, in simulation, atSS and TT process corner.From Figure 5.6, we see that the supply voltage requirement of pruned library is alwaysless than the normal library. From Figure 5.7, we conclude that for the low performancerequirement, normal library is more energy efficient. Also in FF process corner, design ismuch energy efficient all over the performance range.The minimum energy voltage for the CORDIC design was 410-440mV and the minimumenergy consumption was 1.9-2.0 pJ/rotation. The gate count of the CORDIC designusing modified library was 11260 which was approx 32% more than the CORDIC designusing normal library. Thus the CORDIC algorithm was successfully able to operate overa wide voltage range of 270mV to 1.2V.41