Master of Engineering Balram Sahu - Embedded Sensing ...

27 4.4. Behavioral ModelThese values of variables are discrete. If the table lookup does not match with any ofthe variable than two-dimensional interpolation is utilized to provide the resulting timingvalue. For example, let the two index_1 values (total output capacitance) are denotedas x 1 and x 2 , the two index_2 values (Input transition) are denoted as y 1 and y 2 and thecorresponding delay values are denoted as T 11 , T 12 , T 21 and T 22 . Now if the delay valueis required at (x 0 , y 0 ), then the lookup value T 00 can be given by interpolation as:T 00 = x 20 ∗ y 20 ∗ T 11 + x 20 ∗ y 01 ∗ T 12 + x 01 ∗ y 20 ∗ T 21 + x 01 ∗ y 01 ∗ T 22 (4.2)Wherex 01 = (x 0 − x 1 )/(x 2 − x 1 )x 20 = (x 2 − x 0 )/(x 2 − x 1 )y 01 = (y 0 − y 1 )/(y 2 − y 1 )y 20 = (y 2 − y 0 )/(y 2 − y 1 )For Sequential circuits, same timing models are used with some additional constrainedmodels. These constrained models are used for setup and hold time definition. Setuptime, for a positive edge triggered flip-flop, is defined as the data arrival time before thepositive edge of clock that gives the clock-to-Q delay degradation of 10% with respect tothe clock-to-Q delay at a very large data arrival time before the positive edge of clock asshown in Figure 4.7. Similarly hold time, for a positive edge triggered flip-flop, is definedas the change of data time after the positive edge of clock that gives us the clock-to-Qdelay degradation of 10% with respect to the clock-to-Q delay when the data changesafter a long time of positive edge of clock.4.4.2 Power modelPower dissipation in CMOS circuits comes from two components:• Dynamic Power: This is caused by charging and discharging of load capacitanceand due to the short circuit current when NMOS and PMOS, both, are ON.• Leakage Power: The source of leakage power dissipation is sub-threshold leakagecurrent, gate leakage and junction leakage.