Master of Engineering Balram Sahu - Embedded Sensing ...

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CONTENTSiv4 Flip-Flop Characterization 174.1 Requirements on the library . . . . . . . . . . . . . . . . . . . . . . . . . 184.2 Layout Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2.1 Layout Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2.2 Clocked Inverter Flip-flop Layout . . . . . . . . . . . . . . . . . . 204.3 Generation of LEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3.1 Abstract view of Clocked Inverter Flip-flop . . . . . . . . . . . . . 214.4 Behavioral Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.4.1 Timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.4.2 Power model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.4.2.1 Leakage Power . . . . . . . . . . . . . . . . . . . . . . . 284.4.2.2 Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . 285 Simulations and Results 335.1 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.2 Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365.4 Comparison of results with Normal library . . . . . . . . . . . . . . . . . 385.5 The openMSP430 Micro-controller . . . . . . . . . . . . . . . . . . . . . . 406 Conclusions And Scope for Future Work 416.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.2 Scope for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42A Place And Route using SoC Encounter 43A.1 Input Requirements of SoC Encounter . . . . . . . . . . . . . . . . . . . 44A.2 SoC Encounter Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44B LEF File Generation Using Abstract Generator 53
List of Figures2.1 Early measurement of the I D (V GS ) characteristics of a P-channel metalgateMOS transistor (Cleaned-up plot fom [6]) . . . . . . . . . . . . . . . 52.2 NMOS transistor current contribution in sub-threshold. (a) Sub-thresholdcurrent. (b) Gate current. (c) Junction leakage current. . . . . . . . . . . 62.3 Normalized FO4 delay vs. V DD [7] . . . . . . . . . . . . . . . . . . . . . . 82.4 I ON to I OF F ratio of an Inverter . . . . . . . . . . . . . . . . . . . . . . . 92.5 Stacking Factor for I ON and I OF F for 2 and 3 stacked NMOS transistors 92.6 Delay slowdown of Stacked devices . . . . . . . . . . . . . . . . . . . . . 103.1 Pass Transistor Strong and Degraded outputs . . . . . . . . . . . . . . . 113.2 Transmission Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3 Leakage in transmission Gate . . . . . . . . . . . . . . . . . . . . . . . . 123.4 Standard transmission gate CMOS flip-flop . . . . . . . . . . . . . . . . . 133.5 Data Write-Back in Standard Transmission Gate Flip-flop. . . . . . . . . 133.6 Schematic Design of Clocked Inverter Flip-flop . . . . . . . . . . . . . . . 144.1 General Shape of Standard cell core cell . . . . . . . . . . . . . . . . . . 194.2 Definition of routing Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . 194.3 Layout of Clocked Inverter CMOS D Flip-Flop . . . . . . . . . . . . . . . 204.4 Layout of Clocked Inverter CMOS D Flip-Flop . . . . . . . . . . . . . . . 214.5 Timing definitions in standard cell library . . . . . . . . . . . . . . . . . 254.6 Timing Sense of arcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.7 Calculation of Setup Time . . . . . . . . . . . . . . . . . . . . . . . . . . 285.1 Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345.2 Energy characteristics against supply voltage in SS Corner, (For ModifiedLibrary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36v
Page 1: "Minimum Energy Point Operation of
Page 6 and 7: LIST OF FIGURESvi5.3 Normalized Del
Page 8 and 9: viii
Page 12 and 13: 1.4. Thesis Organization 4harvestin
Page 14 and 15: 2.1. Modeling for Sub-threshold ope
Page 16 and 17: 2.2. Challenges in Sub-threshold op
Page 18 and 19: 2.2. Challenges in Sub-threshold op
Page 20 and 21: 3.2. Standard transmission gate CMO
Page 22 and 23: 3.3. Clocked Inverter CMOS Flip-flo
Page 24 and 25: 3.4. Modification in Standard Cell
Page 26 and 27: 4.1. Requirements on the library 18
Page 28 and 29: 4.3. Generation of LEF 20each metal
Page 30 and 31: 4.3. Generation of LEF 2221 PORTLAY
Page 32 and 33: 4.4. Behavioral Model 24127 RECT 3
Page 34 and 35: 4.4. Behavioral Model 26#Falling ed
Page 36 and 37: 4.4. Behavioral Model 28Figure 4.7:
Page 38 and 39: 4.4. Behavioral Model 30v a l u e s
Page 40 and 41: 4.4. Behavioral Model 32
Page 42 and 43: 5.2. Process Flow 34changes and thu
Page 44 and 45: 5.3. Results 365.3 ResultsCORDIC al
Page 46 and 47: 5.4. Comparison of results with Nor
Page 48 and 49: 5.5. The openMSP430 Micro-controlle
Page 50 and 51: 6.2. Scope for Future Work 426.2 Sc
Page 52 and 53: A.1. Input Requirements of SoC Enco
Page 54 and 55:
A.2. SoC Encounter Flow 46design hi
Page 56 and 57:
A.2. SoC Encounter Flow 48Do the se
Page 58 and 59:
A.2. SoC Encounter Flow 50Figure A.
Page 60 and 61:
A.2. SoC Encounter Flow 52
Page 62 and 63:
54The first part can be generated b
Page 64 and 65:
563. Press RUN button and wait unti
Page 66:
BIBLIOGRAPHY 58[11] FARADAY cell li
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